diff options
| author | Jack Koenig | 2021-01-20 18:55:16 -0800 |
|---|---|---|
| committer | Jack Koenig | 2021-01-21 15:36:55 -0800 |
| commit | 8a73362bb6fe87817a1867cc2482c1841f95c077 (patch) | |
| tree | a439d2a5fb52941baeffa22297b38160dc2d1249 /core/src/main/scala/chisel3/Module.scala | |
| parent | b88ae1fb5cd106f114fa2152ac53c197ae69c164 (diff) | |
Remove val io
Chisel projects no longer need -Xsource:2.11 when compiling with Scala
2.12.
Autowrapping of "val io" for compatibility mode Modules is now
implemented using reflection instead of calling the virtual method.
Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
Diffstat (limited to 'core/src/main/scala/chisel3/Module.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/Module.scala | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala index 9a1a0ce1..d34211f1 100644 --- a/core/src/main/scala/chisel3/Module.scala +++ b/core/src/main/scala/chisel3/Module.scala @@ -257,6 +257,11 @@ package experimental { // mainly for compatibility purposes. protected def portsContains(elem: Data): Boolean = _ports contains elem + // This is dangerous because it can be called before the module is closed and thus there could + // be more ports and names have not yet been finalized. + // This should only to be used during the process of closing when it is safe to do so. + private[chisel3] def findPort(name: String): Option[Data] = _ports.find(_.seedOpt.contains(name)) + protected def portsSize: Int = _ports.size /** Generates the FIRRTL Component (Module or Blackbox) of this Module. |
