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(backport #2795) (#2799)
* Don't invalidate ExtModule ports in an explicitInvalidate = true context (#2795)
* Don't invalidate ExtModule ports in an explicitInvalidate = true context
ExtModule ports were previously invalidated in the emitted FIRRTL, which is correct in a NonStrict / `Chisel._` compatibility context but not in newer chisel3 code where `explicitInvalidate = true`.
(cherry picked from commit 8e24a281545d25f6501dcc872eabdfb30bacd69d)
# Conflicts:
# core/src/main/scala/chisel3/BlackBox.scala
* Resolve backport conflicts
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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ExtModule now uses the same namePorts implementation as regular Modules.
Previously, ExtModules only allowed port naming via runtime reflection.
This meant that .suggestName and other naming APIs do not work. It also
breaks FlatIO for ExtModule which is a potential replacement API for
BlackBox's special `val io` handling.
(cherry picked from commit 83cccfb782d9141bf2c843246c2a525c62392924)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(cherry picked from commit f9aee1f72744abc6ee13aafc4d1a51a2783cbab8)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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The new reflection based IO autowrapping for compatibility mode Modules
would previously throw a NullPointerExceptions if any hardware were
constructed in the Module before "val io" was initialized. The logic is
now more robust for this case.
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 50e6099fbecc041973564514e55f67ffe069459b)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Command:
sbt scalafmtAll
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Also clean up deprecation warnings for replacement APIs and add
clarifying ScalaDoc.
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This introduces a new experimental API for module instantiation that disentagles
elaborating the definition (or implementation) from instantiation of
a given module. This solves Chisel's longstanding reliance on
"Deduplication" for generating Verilog with multiple instances of the
same module.
The new API resides in package chisel3.experimental.hierarchy. Please
see the hierarchy ScalaDoc, documentation, and tests for examples of
use.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.
* Add MemTypeBinding for port types of Mems
This binding is similar to the SampleElementBinding for Vecs in that
these Data are not truly hardware, but are represented in the FIRRTL IR
and thus need some representation.
* Call _onModuleClose on unbound Records
This maintains some corner-case behavior that is nevertheless relied
upon. It ensures that refs are set for the elements of Records, even if
they are not bound to any real hardware.
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Co-authored-by: Megan Wachs <megan@sifive.com>
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Chisel projects no longer need -Xsource:2.11 when compiling with Scala
2.12.
Autowrapping of "val io" for compatibility mode Modules is now
implemented using reflection instead of calling the virtual method.
Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
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This is a refinement of the assertion added in #1616 then removed in
#1654. Because Records now set the refs of children upon binding,
later, unbound Records could incorrectly override the refs. The first
set should win.
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It causes issues for some legal (if awkward) patterns. A larger refactor
of when refs are set could reinstate this check.
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* Use Data refs for name prefixing with aggregate elements
Vecs set the refs of their elements upon construction of those elements.
In the past, Records haven't set their elements refs until module close,
but it can be done sooner. Doing it upon binding means that refs will at
least be available for Records used in hardware elements. Since only
bound Data can be connected to anyway, Aggregate elements being
connected to will always have a ref which we can then use for creating
naming prefixes.
* Add tighter correctness checks
* Handle more cases in connection prefixing
Add support for forcing setRef to override a previous setting. This
is only used by BlackBox ports which need to drop their io prefix.
Also add a Try() around Data.bindingToString which sometimes throws
exceptions when being used to .toString a Data in an error message.
* Strip trailing spaces in names in compiler plugin
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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* Deprecate Module.io and BlackBox.io
This is a step toward unification of Module with MultiIOModule.
The future of BlackBox is a bit less clear, but its existing API can be
maintained without the io virtual method.
The trickier API to maintain is auto-IO wrapping for compatibility
Modules and BlackBoxes. This will probably require reflection to support
once the io virtual method is removed.
* Improve deprecation warning for io
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* Rename coreMacros to macros
* Rename chiselFrontend to core
Also make each subproject publish with "chisel3-" as a prefix
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