diff options
| author | mergify[bot] | 2022-05-27 22:06:36 +0000 |
|---|---|---|
| committer | GitHub | 2022-05-27 22:06:36 +0000 |
| commit | 3aed65709aedc22810926751db33fe9ba767a03b (patch) | |
| tree | 28ac9216744c6f2315311674bf87a42846c69289 /core/src/main/scala/chisel3/BlackBox.scala | |
| parent | 2453ac10fae363455398dd1ef5bcdb79e6d23f27 (diff) | |
Make ExtModule port naming consistent with Module (#2548) (#2549)
ExtModule now uses the same namePorts implementation as regular Modules.
Previously, ExtModules only allowed port naming via runtime reflection.
This meant that .suggestName and other naming APIs do not work. It also
breaks FlatIO for ExtModule which is a potential replacement API for
BlackBox's special `val io` handling.
(cherry picked from commit 83cccfb782d9141bf2c843246c2a525c62392924)
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'core/src/main/scala/chisel3/BlackBox.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/BlackBox.scala | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/core/src/main/scala/chisel3/BlackBox.scala b/core/src/main/scala/chisel3/BlackBox.scala index f3fc2711..f618901f 100644 --- a/core/src/main/scala/chisel3/BlackBox.scala +++ b/core/src/main/scala/chisel3/BlackBox.scala @@ -71,11 +71,8 @@ package experimental { val names = nameIds(classOf[ExtModule]) - // Name ports based on reflection - for (port <- getModulePorts) { - require(names.contains(port), s"Unable to name port $port in $this") - port.setRef(ModuleIO(this, _namespace.name(names(port)))) - } + // Ports are named in the same way as regular Modules + namePorts(names) // All suggestions are in, force names to every node. // While BlackBoxes are not supposed to have an implementation, we still need to call |