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AgeCommit message (Expand)Author
2016-10-04Suppress some scala compiler warningsAndrew Waterman
2016-10-04Add CompileOptions implicits to all Module constructors - fix #310. (#311)Jim Lawson
2016-09-29Manual dead code elimination.Jim Lawson
2016-09-29Consolidate CompileOptions and re-enable NotStrict pending macro work.Jim Lawson
2016-09-29Massive rename of CompileOptions.Jim Lawson
2016-09-28Don't use firrtlDirection for direction checks - fix #298.Jim Lawson
2016-09-26Add Strict default for compile optionsducky
2016-09-23Merge branch 'master' into gsdtJim Lawson
2016-09-23Merge pull request #291 from ucb-bar/utilscaladocsJim Lawson
2016-09-21Improved scaladoc in utils and friendsducky
2016-09-21Expose FIRRTL asClock constructAndrew Waterman
2016-09-21Make implicit clock name consistent (#288)Andrew Waterman
2016-09-15add optional directionality assumption to BiConnect.elemConnectJim Lawson
2016-09-15Revert "Add direction-only (no width) UInt factory method."Jim Lawson
2016-09-15Add direction-only (no width) UInt factory method.Jim Lawson
2016-09-15Merge branch 'master' into gsdtJim Lawson
2016-09-09Convert to NotStrict for internal connection checks.Jim Lawson
2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
2016-09-07Add Printable (#270)Jack Koenig
2016-09-02Add/cleanup UInt/SInt factory methods.Jim Lawson
2016-09-02Deprecate asBits; modify deprecation warnings accordinglyAndrew Waterman
2016-09-01Remove O(n^2) code in Vec.apply(Seq)Andrew Waterman
2016-09-01Deprecate Vec.fill() offering Vec(Seq.fill()).Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
2016-08-31Check that Vecs have homogeneous typesAndrew Waterman
2016-08-30Merge branch 'master' into gsdtJim Lawson
2016-08-30Use correct case for Strict/NotStrict compile options.Jim Lawson
2016-08-29Check module-specific compile options.Jim Lawson
2016-08-29Rename CompileOptions implicit objects.Jim Lawson
2016-08-29Pass compileOptions as an implicit Module parameter.Jim Lawson
2016-08-29Rename individual compile options.Jim Lawson
2016-08-25Use bulkConnect in Vec,fill if any (flattened) element of the Vec has a direc...Jim Lawson
2016-08-24Per Chisel meeting.chick
2016-08-23Swap name of compileOption "assumeNoDirectionIsOutput" to "assumeNoDirectionI...Jim Lawson
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
2016-08-19Restore immutability of direction overrides.Jim Lawson
2016-08-19Simplify autioIOWrap code in computePorts().Jim Lawson
2016-08-18Add assumeNoDirectionIsOutput.Jim Lawson
2016-08-18Use isFirrtlFlipped() to determine port direction.Jim Lawson
2016-08-18Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_testsJim Lawson
2016-08-17Rocket-chip updates.Jim Lawson
2016-08-17Reduce rocket-chip elaboration errors.Jim Lawson
2016-08-16Add component to signature.Jim Lawson
2016-08-16Provide public SignalID trait to be used to conjure up a signal identifier.Jim Lawson
2016-08-16Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-15Make "def width" a private API; expose isWidthKnown instead (#257)Andrew Waterman
2016-08-12Use compileOptions to determine if Missing...FieldExceptions are thrown.Jim Lawson
2016-08-12Merge branch 'compile_options' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-12Add support for per-Module compilation options.Jim Lawson
2016-08-11Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
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