Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_tests

Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk

14 files changed, 1184 insertions, 180 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 15643ac8..03c84827 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -14,7 +14,7 @@ import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransfo
 /** An abstract class for data types that solely consist of (are an aggregate
   * of) other Data objects.
   */
-sealed abstract class Aggregate(dirArg: Direction) extends Data(dirArg) {
+sealed abstract class Aggregate extends Data {
   private[core] def cloneTypeWidth(width: Width): this.type = cloneType
   private[core] def width: Width = flatten.map(_.width).reduce(_ + _)
 }
@@ -24,10 +24,10 @@ object Vec {
     *
     * @note elements are NOT assigned by default and have no value
     */
-  def apply[T <: Data](n: Int, gen: T): Vec[T] = new Vec(gen.cloneType, n)
+  def apply[T <: Data](n: Int, gen: T): Vec[T] = new Vec(gen, n)
 
   @deprecated("Vec argument order should be size, t; this will be removed by the official release", "chisel3")
-  def apply[T <: Data](gen: T, n: Int): Vec[T] = new Vec(gen.cloneType, n)
+  def apply[T <: Data](gen: T, n: Int): Vec[T] = new Vec(gen, n)
 
   /** Creates a new [[Vec]] composed of elements of the input Seq of [[Data]]
     * nodes.
@@ -104,29 +104,41 @@ object Vec {
   * @note Vecs, unlike classes in Scala's collection library, are propagated
   * intact to FIRRTL as a vector type, which may make debugging easier
   */
-sealed class Vec[T <: Data] private (gen: => T, val length: Int)
-    extends Aggregate(gen.dir) with VecLike[T] {
+sealed class Vec[T <: Data] private (gen: T, val length: Int)
+    extends Aggregate with VecLike[T] {
   // Note: the constructor takes a gen() function instead of a Seq to enforce
   // that all elements must be the same and because it makes FIRRTL generation
   // simpler.
+  private val self: Seq[T] = Vector.fill(length)(gen.chiselCloneType)
 
-  private val self = IndexedSeq.fill(length)(gen)
+  /**
+  * sample_element 'tracks' all changes to the elements of self.
+  * For consistency, sample_element is always used for creating dynamically
+  * indexed ports and outputing the FIRRTL type.
+  *
+  * Needed specifically for the case when the Vec is length 0.
+  */
+  private[core] val sample_element: T = gen.chiselCloneType
 
-  override def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this := that
+  // allElements current includes sample_element
+  // This is somewhat weird although I think the best course of action here is
+  // to deprecate allElements in favor of dispatched functions to Data or
+  // a pattern matched recursive descent
+  private[chisel3] final def allElements: Seq[Element] =
+    (sample_element +: self).flatMap(_.allElements)
 
   /** Strong bulk connect, assigning elements in this Vec from elements in a Seq.
     *
     * @note the length of this Vec must match the length of the input Seq
     */
-  def <> (that: Seq[T])(implicit sourceInfo: SourceInfo): Unit = this := that
+  def <> (that: Seq[T])(implicit sourceInfo: SourceInfo): Unit = {
+    require(this.length == that.length)
+    for ((a, b) <- this zip that)
+      a <> b
+  }
 
   // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data
-  def <> (that: Vec[T])(implicit sourceInfo: SourceInfo): Unit = this := that.asInstanceOf[Data]
-
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: Vec[_] => this connect that
-    case _ => this badConnect that
-  }
+  def <> (that: Vec[T])(implicit sourceInfo: SourceInfo): Unit = this bulkConnect that.asInstanceOf[Data]
 
   /** Strong bulk connect, assigning elements in this Vec from elements in a Seq.
     *
@@ -144,9 +156,17 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
   /** Creates a dynamically indexed read or write accessor into the array.
     */
   def apply(idx: UInt): T = {
-    val x = gen
-    x.setRef(this, idx)
-    x
+    Binding.checkSynthesizable(idx ,s"'idx' ($idx)")
+    val port = sample_element.chiselCloneType
+    port.setRef(this, idx) //TODO(twigg): This is a bit too magical
+
+    // Bind each element of port to being whatever the base type is
+    // Using the head element as the sample_element
+    for((port_elem, model_elem) <- port.allElements zip sample_element.allElements) {
+      port_elem.binding = model_elem.binding
+    }
+
+    port
   }
 
   /** Creates a statically indexed read or write accessor into the array.
@@ -159,11 +179,11 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
   @deprecated("Use Vec.apply instead", "chisel3")
   def write(idx: UInt, data: T): Unit = apply(idx).:=(data)(DeprecatedSourceInfo)
 
-  override def cloneType: this.type =
+  override def cloneType: this.type = {
     Vec(length, gen).asInstanceOf[this.type]
+  }
 
-  private val t = gen
-  private[chisel3] def toType: String = s"${t.toType}[$length]"
+  private[chisel3] def toType: String = s"${sample_element.toType}[$length]"
   private[chisel3] lazy val flatten: IndexedSeq[Bits] =
     (0 until length).flatMap(i => this.apply(i).flatten)
 
@@ -256,7 +276,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
   * Usage: extend this class (either as an anonymous or named class) and define
   * members variables of [[Data]] subtypes to be elements in the Bundle.
   */
-class Bundle extends Aggregate(NO_DIR) {
+class Bundle extends Aggregate {
   private val _namespace = Builder.globalNamespace.child
 
   // TODO: replace with better defined FIRRTL weak-connect operator
@@ -272,13 +292,6 @@ class Bundle extends Aggregate(NO_DIR) {
     * mySubModule.io <> io
     * }}}
     */
-  override def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: Bundle => this bulkConnect that
-    case _ => this badConnect that
-  }
-
-  // TODO: replace with better defined FIRRTL strong-connect operator
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this <> that
 
   lazy val elements: ListMap[String, Data] = ListMap(namedElts:_*)
 
@@ -333,7 +346,7 @@ class Bundle extends Aggregate(NO_DIR) {
   }
   private[chisel3] def toType = {
     def eltPort(elt: Data): String = {
-      val flipStr = if (elt.isFlip) "flip " else ""
+      val flipStr: String = if(Data.isFirrtlFlipped(elt)) "flip " else ""
       s"${flipStr}${elt.getRef.name} : ${elt.toType}"
     }
     s"{${namedElts.reverse.map(e => eltPort(e._2)).mkString(", ")}}"
@@ -343,6 +356,8 @@ class Bundle extends Aggregate(NO_DIR) {
     namedElts += name -> elt
   private[chisel3] override def _onModuleClose: Unit = // scalastyle:ignore method.name
     for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) }
+    
+  private[chisel3] final def allElements: Seq[Element] = namedElts.flatMap(_._2.allElements)
 
   override def cloneType : this.type = {
     // If the user did not provide a cloneType method, try invoking one of
@@ -374,5 +389,5 @@ class Bundle extends Aggregate(NO_DIR) {
 
 private[core] object Bundle {
   val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits",
-                      "widthOption")
+                      "widthOption", "chiselCloneType")
 }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
index 9111a334..db62f4a8 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
@@ -50,12 +50,12 @@ object assert { // scalastyle:ignore object.name
   }
 
   def apply_impl_do(cond: Bool, line: String, message: Option[String])(implicit sourceInfo: SourceInfo) {
-    when (!(cond || Builder.dynamicContext.currentModule.get.reset)) {
+    when (!(cond || Builder.forcedModule.reset)) {
       message match {
         case Some(str) => printf.printfWithoutReset(s"Assertion failed: $str\n    at $line\n")
         case None => printf.printfWithoutReset(s"Assertion failed\n    at $line\n")
       }
-      pushCommand(Stop(sourceInfo, Node(Builder.dynamicContext.currentModule.get.clock), 1))
+      pushCommand(Stop(sourceInfo, Node(Builder.forcedModule.clock), 1))
     }
   }
 
@@ -75,8 +75,8 @@ object assert { // scalastyle:ignore object.name
 object stop { // scalastyle:ignore object.name
   /** Terminate execution with a failure code. */
   def apply(code: Int)(implicit sourceInfo: SourceInfo): Unit = {
-    when (!Builder.dynamicContext.currentModule.get.reset) {
-      pushCommand(Stop(sourceInfo, Node(Builder.dynamicContext.currentModule.get.clock), code))
+    when (!Builder.forcedModule.reset) {
+      pushCommand(Stop(sourceInfo, Node(Builder.forcedModule.clock), code))
     }
   }
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
new file mode 100644
index 00000000..c40b85ad
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -0,0 +1,224 @@
+package chisel3.core
+
+import chisel3.internal.Builder.{compileOptions, pushCommand}
+import chisel3.internal.firrtl.Connect
+import scala.language.experimental.macros
+import chisel3.internal.sourceinfo._
+
+/**
+* BiConnect.connect executes a bidirectional connection element-wise.
+*
+* Note that the arguments are left and right (not source and sink) so the
+* intent is for the operation to be commutative.
+*
+* The connect operation will recurse down the left Data (with the right Data).
+* An exception will be thrown if a movement through the left cannot be matched
+* in the right (or if the right side has extra fields).
+*
+* See elemConnect for details on how the root connections are issued.
+*
+*/
+
+object BiConnect {
+  // These are all the possible exceptions that can be thrown.
+  case class BiConnectException(message: String) extends Exception(message)
+  // These are from element-level connection
+  def BothDriversException =
+    BiConnectException(": Both Left and Right are drivers")
+  def NeitherDriverException =
+    BiConnectException(": Neither Left nor Right is a driver")
+  def UnknownDriverException =
+    BiConnectException(": Locally unclear whether Left or Right (both internal)")
+  def UnknownRelationException =
+    BiConnectException(": Left or Right unavailable to current module.")
+  // These are when recursing down aggregate types
+  def MismatchedVecException =
+    BiConnectException(": Left and Right are different length Vecs.")
+  def MissingLeftFieldException(field: String) =
+    BiConnectException(s".$field: Left Bundle missing field ($field).")
+  def MissingRightFieldException(field: String) =
+    BiConnectException(s": Right Bundle missing field ($field).")
+  def MismatchedException(left: String, right: String) =
+    BiConnectException(s": Left ($left) and Right ($right) have different types.")
+
+  /** This function is what recursively tries to connect a left and right together
+  *
+  * There is some cleverness in the use of internal try-catch to catch exceptions
+  * during the recursive decent and then rethrow them with extra information added.
+  * This gives the user a 'path' to where in the connections things went wrong.
+  */
+  def connect(sourceInfo: SourceInfo, left: Data, right: Data, context_mod: Module): Unit =
+    (left, right) match {
+      // Handle element case (root case)
+      case (left_e: Element, right_e: Element) => {
+        elemConnect(sourceInfo, left_e, right_e, context_mod)
+        // TODO(twigg): Verify the element-level classes are connectable
+      }
+      // Handle Vec case
+      case (left_v: Vec[Data @unchecked], right_v: Vec[Data @unchecked]) => {
+        if(left_v.length != right_v.length) { throw MismatchedVecException }
+        for(idx <- 0 until left_v.length) {
+          try {
+            connect(sourceInfo, left_v(idx), right_v(idx), context_mod)
+          } catch {
+            case BiConnectException(message) => throw BiConnectException(s"($idx)$message")
+          }
+        }
+      }
+      // Handle Bundle case
+      case (left_b: Bundle, right_b: Bundle) => {
+        // Verify right has no extra fields that left doesn't have
+        for((field, right_sub) <- right_b.elements) {
+          if(!left_b.elements.isDefinedAt(field)) {
+            if (compileOptions.connectFieldsMustMatch) {
+              throw MissingLeftFieldException(field)
+            }
+          }
+        }
+        // For each field in left, descend with right
+        for((field, left_sub) <- left_b.elements) {
+          try {
+            right_b.elements.get(field) match {
+              case Some(right_sub) => connect(sourceInfo, left_sub, right_sub, context_mod)
+              case None => {
+                if (compileOptions.connectFieldsMustMatch) {
+                  throw MissingRightFieldException(field)
+                }
+              }
+            }
+          } catch {
+            case BiConnectException(message) => throw BiConnectException(s".$field$message")
+          }
+        }
+      }
+      // Left and right are different subtypes of Data so fail
+      case (left, right) => throw MismatchedException(left.toString, right.toString)
+    }
+
+  // These functions (finally) issue the connection operation
+  // Issue with right as sink, left as source
+  private def issueConnectL2R(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = {
+    pushCommand(Connect(sourceInfo, right.lref, left.ref))
+  }
+  // Issue with left as sink, right as source
+  private def issueConnectR2L(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = {
+    pushCommand(Connect(sourceInfo, left.lref, right.ref))
+  }
+
+  // This function checks if element-level connection operation allowed.
+  // Then it either issues it or throws the appropriate exception.
+  def elemConnect(implicit sourceInfo: SourceInfo, left: Element, right: Element, context_mod: Module): Unit = {
+    import Direction.{Input, Output} // Using extensively so import these
+    // If left or right have no location, assume in context module
+    // This can occur if one of them is a literal, unbound will error previously
+    val left_mod: Module  = left.binding.location.getOrElse(context_mod)
+    val right_mod: Module = right.binding.location.getOrElse(context_mod)
+
+    val left_direction: Option[Direction] = left.binding.direction
+    val right_direction: Option[Direction] = right.binding.direction
+    // None means internal
+
+    // CASE: Context is same module as left node and right node is in a child module
+    if( (left_mod == context_mod) &&
+        (right_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, right node better be a port node and thus have a direction hint
+      (left_direction, right_direction) match {
+        //    CURRENT MOD   CHILD MOD
+        case (Some(Input),  Some(Input))  => issueConnectL2R(left, right)
+        case (None,         Some(Input))  => issueConnectL2R(left, right)
+
+        case (Some(Output), Some(Output)) => issueConnectR2L(left, right)
+        case (None,         Some(Output)) => issueConnectR2L(left, right)
+
+        case (Some(Input),  Some(Output)) => throw BothDriversException
+        case (Some(Output), Some(Input))  => throw NeitherDriverException
+        case (_,            None)         => throw UnknownRelationException
+      }
+    }
+
+    // CASE: Context is same module as right node and left node is in child module
+    else if( (right_mod == context_mod) &&
+             (left_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, left node better be a port node and thus have a direction hint
+      (left_direction, right_direction) match {
+        //    CHILD MOD     CURRENT MOD
+        case (Some(Input),  Some(Input))  => issueConnectR2L(left, right)
+        case (Some(Input),  None)         => issueConnectR2L(left, right)
+
+        case (Some(Output), Some(Output)) => issueConnectL2R(left, right)
+        case (Some(Output), None)         => issueConnectL2R(left, right)
+
+        case (Some(Input),  Some(Output)) => throw NeitherDriverException
+        case (Some(Output), Some(Input))  => throw BothDriversException
+        case (None, _)                    => throw UnknownRelationException
+      }
+    }
+
+    // CASE: Context is same module that both left node and right node are in
+    else if( (context_mod == left_mod) && (context_mod == right_mod) ) {
+      (left_direction, right_direction) match {
+        //    CURRENT MOD   CURRENT MOD
+        case (Some(Input),  Some(Output)) => issueConnectL2R(left, right)
+        case (Some(Input),  None)         => issueConnectL2R(left, right)
+        case (None,         Some(Output)) => issueConnectL2R(left, right)
+
+        case (Some(Output), Some(Input))  => issueConnectR2L(left, right)
+        case (Some(Output), None)         => issueConnectR2L(left, right)
+        case (None,         Some(Input))  => issueConnectR2L(left, right)
+
+        case (Some(Input),  Some(Input))  => {
+          if (compileOptions.portDeterminesDirection)
+          (left.binding, right.binding) match {
+            case (PortBinding(_, _), PortBinding(_, _)) => throw BothDriversException
+            case (PortBinding(_, _), _) => issueConnectL2R(left, right)
+            case (_, PortBinding(_, _)) => issueConnectR2L(left, right)
+            case _ => throw BothDriversException
+          } else {
+            throw BothDriversException
+          }
+        }
+        case (Some(Output), Some(Output)) => {
+          if (compileOptions.portDeterminesDirection)
+            (left.binding, right.binding) match {
+              case (PortBinding(_, _), PortBinding(_, _)) => throw BothDriversException
+              case (PortBinding(_, _), _) => issueConnectR2L(left, right)
+              case (_, PortBinding(_, _)) => issueConnectL2R(left, right)
+              case _ => throw BothDriversException
+            } else {
+            throw BothDriversException
+          }
+        }
+        case (None,         None)         => {
+          if (compileOptions.assumeLHSIsOutput) {
+            issueConnectR2L(left, right)
+          } else {
+            throw UnknownDriverException
+          }
+        }
+      }
+    }
+
+    // CASE: Context is the parent module of both the module containing left node
+    //                                        and the module containing right node
+    //   Note: This includes case when left and right in same module but in parent
+    else if( (left_mod._parent.map(_ == context_mod).getOrElse(false)) &&
+             (right_mod._parent.map(_ == context_mod).getOrElse(false))
+    ) {
+      // Thus both nodes must be ports and have a direction hint
+      (left_direction, right_direction) match {
+        //    CHILD MOD     CHILD MOD
+        case (Some(Input),  Some(Output)) => issueConnectR2L(left, right)
+        case (Some(Output), Some(Input))  => issueConnectL2R(left, right)
+
+        case (Some(Input),  Some(Input))  => throw NeitherDriverException
+        case (Some(Output), Some(Output)) => throw BothDriversException
+        case (_, None)                    => throw UnknownRelationException
+        case (None, _)                    => throw UnknownRelationException
+      }
+    }
+
+    // Not quite sure where left and right are compared to current module
+    // so just error out
+    else throw UnknownRelationException
+  }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala
new file mode 100644
index 00000000..c7346dce
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala
@@ -0,0 +1,64 @@
+package chisel3.core
+
+/**
+* A Binder is a function from UnboundBinding to some Binding.
+*
+* These are used exclusively by Binding.bind and sealed in order to keep
+* all of them in one place. There are two flavors of Binders:
+* Non-terminal (returns another UnboundBinding): These are used to reformat an
+*   UnboundBinding (like setting direction) before it is terminally bound.
+* Terminal (returns any other Binding): Due to the nature of Bindings, once a
+*   Data is bound to anything but an UnboundBinding, it is forever locked to
+*   being that type (as it now represents something in the hardware graph).
+*
+* Note that some Binders require extra arguments to be constructed, like the
+* enclosing Module.
+*/
+
+sealed trait Binder[Out <: Binding] extends Function1[UnboundBinding, Out]{
+  def apply(in: UnboundBinding): Out
+}
+
+// THE NON-TERMINAL BINDERS
+// These 'rebind' to another unbound node of different direction!
+case object InputBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(Some(Direction.Input))
+}
+case object OutputBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(Some(Direction.Output))
+}
+case object FlippedBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(in.direction.map(_.flip))
+  // TODO(twigg): flipping a None should probably be a warning/error
+}
+// The need for this should be transient.
+case object NoDirectionBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(None)
+}
+
+// THE TERMINAL BINDERS
+case object LitBinder extends Binder[LitBinding] {
+  def apply(in: UnboundBinding) = LitBinding()
+}
+
+case class MemoryPortBinder(enclosure: Module) extends Binder[MemoryPortBinding] {
+  def apply(in: UnboundBinding) = MemoryPortBinding(enclosure)
+}
+
+case class OpBinder(enclosure: Module) extends Binder[OpBinding] {
+  def apply(in: UnboundBinding) = OpBinding(enclosure)
+}
+
+// Notice how PortBinder uses the direction of the UnboundNode
+case class PortBinder(enclosure: Module) extends Binder[PortBinding] {
+  def apply(in: UnboundBinding) = PortBinding(enclosure, in.direction)
+}
+
+case class RegBinder(enclosure: Module) extends Binder[RegBinding] {
+  def apply(in: UnboundBinding) = RegBinding(enclosure)
+}
+
+case class WireBinder(enclosure: Module) extends Binder[WireBinding] {
+  def apply(in: UnboundBinding) = WireBinding(enclosure)
+}
+
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
new file mode 100644
index 00000000..da678fed
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -0,0 +1,211 @@
+package chisel3.core
+
+import chisel3.internal.Builder.compileOptions
+
+/**
+ * The purpose of a Binding is to indicate what type of hardware 'entity' a
+ * specific Data's leaf Elements is actually bound to. All Data starts as being
+ * Unbound (and the whole point of cloneType is to return an unbound version).
+ * Then, specific API calls take a Data, and return a bound version (either by
+ * binding the original model or cloneType then binding the clone). For example,
+ * Reg[T<:Data](...) returns a T bound to RegBinding.
+ *
+ * It is considered invariant that all Elements of a single Data are bound to
+ * the same concrete type of Binding.
+ *
+ * These bindings can be checked (e.g. checkSynthesizable) to make sure certain
+ * operations are valid. For example, arithemetic operations or connections can
+ * only be executed between synthesizable nodes. These checks are to avoid
+ * undefined reference errors.
+ *
+ * Bindings can carry information about the particular element in the graph it
+ * represents like:
+ * - For ports (and unbound), the 'direction'
+ * - For (relevant) synthesizable nodes, the enclosing Module
+ *
+ * TODO(twigg): Enrich the bindings to carry more information like the hosting
+ * module (when applicable), direction (when applicable), literal info (when
+ * applicable). Can ensure applicable data only stored on relevant nodes. e.g.
+ * literal info on LitBinding, direction info on UnboundBinding and PortBinding,
+ * etc.
+ *
+ * TODO(twigg): Currently, bindings only apply at the Element level and an
+ * Aggregate is considered bound via its elements. May be appropriate to allow
+ * Aggregates to be bound along with the Elements. However, certain literal and
+ * port direction information doesn't quite make sense in aggregates. This would
+ * elegantly handle the empty Vec or Bundle problem though.
+ *
+ * TODO(twigg): Binding is currently done via allElements. It may be more
+ * elegant if this was instead done as a more explicit tree walk as that allows
+ * for better errors.
+ */
+
+object Binding {
+  // Two bindings are 'compatible' if they are the same type.
+  // Check currently kind of weird: just ensures same class
+  private def compatible(a: Binding, b: Binding): Boolean = a.getClass == b.getClass
+  private def compatible(nodes: Seq[Binding]): Boolean =
+    if(nodes.size > 1)
+      (for((a,b) <- nodes zip nodes.tail) yield compatible(a,b))
+      .fold(true)(_&&_)
+    else true
+
+  case class BindingException(message: String) extends Exception(message)
+  def AlreadyBoundException(binding: String) = BindingException(s": Already bound to $binding")
+  def NotSynthesizableException = BindingException(s": Not bound to synthesizable node, currently only Type description")
+
+  // This recursively walks down the Data tree to look at all the leaf 'Element's
+  // Will build up an error string in case something goes wrong
+  // TODO(twigg): Make member function of Data.
+  //   Allows oddities like sample_element to be better hidden
+  private def walkToBinding(target: Data, checker: Element=>Unit): Unit = target match {
+    case (element: Element) => checker(element)
+    case (vec: Vec[Data @unchecked]) => {
+      try walkToBinding(vec.sample_element, checker)
+      catch {
+        case BindingException(message) => throw BindingException(s"(*)$message")
+      }
+      for(idx <- 0 until vec.length) {
+        try walkToBinding(vec(idx), checker)
+        catch {
+          case BindingException(message) => throw BindingException(s"($idx)$message")
+        }
+      }
+    }
+    case (bundle: Bundle) => {
+      for((field, subelem) <- bundle.elements) {
+        try walkToBinding(subelem, checker)
+        catch {
+          case BindingException(message) => throw BindingException(s".$field$message")
+        }
+      }
+    }
+  }
+
+  // Use walkToBinding to actually rebind the node type
+  def bind[T<:Data](target: T, binder: Binder[_<:Binding], error_prelude: String): target.type = {
+    try walkToBinding(
+      target,
+      element => element.binding match {
+        case unbound @ UnboundBinding(_) => {
+          element.binding = binder(unbound)
+        }
+          // If autoIOWrap is enabled and we're rebinding a PortBinding, just ignore the rebinding.
+        case portBound @ PortBinding(_, _) if (compileOptions.autoIOWrap && binder.isInstanceOf[PortBinder]) =>
+        case binding => throw AlreadyBoundException(binding.toString)
+      }
+    )
+    catch {
+      case BindingException(message) => throw BindingException(s"$error_prelude$message")
+    }
+    target
+  }
+
+  // Excepts if any root element is already bound
+  def checkUnbound(target: Data, error_prelude: String): Unit = {
+    try walkToBinding(
+      target,
+      element => element.binding match {
+        case unbound @ UnboundBinding(_) => {}
+        case binding => throw AlreadyBoundException(binding.toString)
+      }
+    )
+    catch {
+      case BindingException(message) => throw BindingException(s"$error_prelude$message")
+    }
+  }
+
+  // Excepts if any root element is unbound and thus not on the hardware graph
+  def checkSynthesizable(target: Data, error_prelude: String): Unit = {
+    // This is called if we support autoIOWrap
+    def elementOfIO(element: Element): Boolean = {
+      element._parent match {
+        case None => false
+        case Some(x: Module) => {
+          // Have we defined the IO ports for this module? If not, do so now.
+          if (!x.ioDefined) {
+            x.computePorts
+            element.binding match {
+              case SynthesizableBinding() => true
+              case _ => false
+            }
+          } else {
+            // io.flatten eliminates Clock elements, so we need to use io.allElements
+            val ports = x.io.allElements
+            val isIOElement = ports.contains(element) || element == x.clock || element == x.reset
+            isIOElement
+          }
+        }
+      }
+    }
+    try walkToBinding(
+      target,
+      element => element.binding match {
+        case SynthesizableBinding() => {} // OK
+        case binding =>
+          // The following kludge is an attempt to provide backward compatibility
+          // It should be done at at higher level.
+          if (!(compileOptions.autoIOWrap && elementOfIO(element)))
+            throw NotSynthesizableException
+          else
+            Binding.bind(element, PortBinder(element._parent.get), "Error: IO")
+      }
+    )
+    catch {
+      case BindingException(message) => throw BindingException(s"$error_prelude$message")
+    }
+  }
+}
+
+// Location refers to 'where' in the Module hierarchy this lives
+sealed trait Binding {
+  def location: Option[Module]
+  def direction: Option[Direction]
+}
+
+// Constrained-ness refers to whether 'bound by Module boundaries'
+// An unconstrained binding, like a literal, can be read by everyone
+sealed trait UnconstrainedBinding extends Binding {
+  def location = None
+}
+// A constrained binding can only be read/written by specific modules
+// Location will track where this Module is
+sealed trait ConstrainedBinding extends Binding {
+  def enclosure: Module
+  def location = Some(enclosure)
+}
+
+// An undirectioned binding means the element represents an internal node
+//   with no meaningful concept of a direction
+sealed trait UndirectionedBinding extends Binding { def direction = None }
+
+// This is the default binding, represents data not yet positioned in the graph
+case class UnboundBinding(direction: Option[Direction])
+    extends Binding with UnconstrainedBinding
+
+
+// A synthesizable binding is 'bound into' the hardware graph
+object SynthesizableBinding {
+  def unapply(target: Binding): Boolean = target.isInstanceOf[SynthesizableBinding]
+  // Type check OK because Binding and SynthesizableBinding is sealed
+}
+sealed trait SynthesizableBinding extends Binding
+case class LitBinding() // will eventually have literal info
+    extends SynthesizableBinding with UnconstrainedBinding with UndirectionedBinding
+
+case class MemoryPortBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
+
+// TODO(twigg): Ops between unenclosed nodes can also be unenclosed
+// However, Chisel currently binds all op results to a module
+case class OpBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
+
+case class PortBinding(enclosure: Module, direction: Option[Direction])
+    extends SynthesizableBinding with ConstrainedBinding
+
+case class RegBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
+
+case class WireBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 015b9dfb..c2621251 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -14,13 +14,37 @@ import chisel3.internal.firrtl.PrimOp._
 /** Element is a leaf data type: it cannot contain other Data objects. Example
   * uses are for representing primitive data types, like integers and bits.
   */
-abstract class Element(dirArg: Direction, private[core] val width: Width) extends Data(dirArg)
+abstract class Element(private[core] val width: Width) extends Data {
+  /**
+   * Elements can actually be bound to the hardware graph and thus must store
+   * that binding information.
+   */
+  private[this] var _binding: Binding = UnboundBinding(None)
+  // Define setter/getter pairing
+  // Can only bind something that has not yet been bound.
+  private[core] def binding_=(target: Binding): Unit = _binding match {
+    case UnboundBinding(_) => {
+      _binding = target
+      _binding
+    }
+    case _ => throw Binding.AlreadyBoundException(_binding.toString)
+      // Other checks should have caught this.
+  }
+  private[core] def binding = _binding
+
+  /** Return the binding for some bits. */
+  def dir: Direction = binding.direction.getOrElse(Direction.Unspecified)
+
+  private[chisel3] final def allElements: Seq[Element] = Seq(this)
+  def widthKnown: Boolean = width.known
+  def name: String = getRef.name
+}
 
 /** A data type for values represented by a single bitvector. Provides basic
   * bitwise operations.
   */
-sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: Option[LitArg])
-    extends Element(dirArg, width) {
+sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
+    extends Element(width) {
   // TODO: perhaps make this concrete?
   // Arguments for: self-checking code (can't do arithmetic on bits)
   // Arguments against: generates down to a FIRRTL UInt anyways
@@ -31,8 +55,6 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
 
   def cloneType: this.type = cloneTypeWidth(width)
 
-  override def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this := that
-
   final def tail(n: Int): UInt = macro SourceInfoTransform.nArg
   final def head(n: Int): UInt = macro SourceInfoTransform.nArg
 
@@ -52,7 +74,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
       case KnownWidth(x) => require(x >= n, s"Can't head($n) for width $x < $n")
       case UnknownWidth() =>
     }
-    binop(sourceInfo, UInt(width = n), HeadOp, n)
+    binop(sourceInfo, UInt(Width(n)), HeadOp, n)
   }
 
   /** Returns the specified bit on this wire as a [[Bool]], statically
@@ -67,6 +89,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
     if (isLit()) {
       Bool(((litValue() >> x.toInt) & 1) == 1)
     } else {
+      Binding.checkSynthesizable(this, s"'this' ($this)")
       pushOp(DefPrim(sourceInfo, Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x)))
     }
   }
@@ -108,7 +131,8 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
     if (isLit()) {
       UInt((litValue >> y) & ((BigInt(1) << w) - 1), w)
     } else {
-      pushOp(DefPrim(sourceInfo, UInt(width = w), BitsExtractOp, this.ref, ILit(x), ILit(y)))
+      Binding.checkSynthesizable(this, s"'this' ($this)")
+      pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y)))
     }
   }
 
@@ -118,17 +142,28 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   final def do_apply(x: BigInt, y: BigInt)(implicit sourceInfo: SourceInfo): UInt =
     apply(x.toInt, y.toInt)
 
-  private[core] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T =
+  private[core] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
     pushOp(DefPrim(sourceInfo, dest, op, this.ref))
-  private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T =
+  }
+  private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
     pushOp(DefPrim(sourceInfo, dest, op, this.ref, ILit(other)))
-  private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T =
+  }
+  private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
+    Binding.checkSynthesizable(other, s"'other' ($other)")
     pushOp(DefPrim(sourceInfo, dest, op, this.ref, other.ref))
-
-  private[core] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool =
+  }
+  private[core] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
+    Binding.checkSynthesizable(other, s"'other' ($other)")
     pushOp(DefPrim(sourceInfo, Bool(), op, this.ref, other.ref))
-  private[core] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool =
+  }
+  private[core] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
     pushOp(DefPrim(sourceInfo, Bool(), op, this.ref))
+  }
 
   /** Returns this wire zero padded up to the specified width.
     *
@@ -224,9 +259,9 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
 
   def do_toBool(implicit sourceInfo: SourceInfo): Bool = {
     width match {
-    case KnownWidth(1) => this(0)
-    case _ => throwException(s"can't covert UInt<$width> to Bool")
-  }
+      case KnownWidth(1) => this(0)
+      case _ => throwException(s"can't covert UInt<$width> to Bool")
+    }
   }
 
   /** Returns this wire concatenated with `other`, where this wire forms the
@@ -347,20 +382,16 @@ abstract trait Num[T <: Data] {
 /** A data type for unsigned integers, represented as a binary bitvector.
   * Defines arithmetic operations between other integer types.
   */
-sealed class UInt private[core] (dir: Direction, width: Width, lit: Option[ULit] = None)
-    extends Bits(dir, width, lit) with Num[UInt] {
+sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
+    extends Bits(width, lit) with Num[UInt] {
+
   private[core] override def cloneTypeWidth(w: Width): this.type =
-    new UInt(dir, w).asInstanceOf[this.type]
+    new UInt(w).asInstanceOf[this.type]
   private[chisel3] def toType = s"UInt$width"
 
   override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
     UInt(value, width).asInstanceOf[this.type]
 
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: UInt => this connect that
-    case _ => this badConnect that
-  }
-
   // TODO: refactor to share documentation with Num or add independent scaladoc
   final def unary_- (): UInt = macro SourceInfoTransform.noArg
   final def unary_-% (): UInt = macro SourceInfoTransform.noArg
@@ -433,7 +464,7 @@ sealed class UInt private[core] (dir: Direction, width: Width, lit: Option[ULit]
 
   final def unary_! () : Bool = macro SourceInfoTransform.noArg
 
-  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === Bits(0)
+  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === UInt(0, 1)
 
   override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): UInt =
     binop(sourceInfo, UInt(this.width + that), ShiftLeftOp, that)
@@ -475,29 +506,48 @@ sealed class UInt private[core] (dir: Direction, width: Width, lit: Option[ULit]
 // This is currently a factory because both Bits and UInt inherit it.
 private[core] sealed trait UIntFactory {
   /** Create a UInt type with inferred width. */
-  def apply(): UInt = apply(NO_DIR, Width())
-  /** Create a UInt type or port with fixed width. */
-  def apply(dir: Direction = NO_DIR, width: Int): UInt = apply(dir, Width(width))
-  /** Create a UInt port with inferred width. */
-  def apply(dir: Direction): UInt = apply(dir, Width())
-
-  /** Create a UInt literal with inferred width. */
-  def apply(value: BigInt): UInt = apply(value, Width())
+  def apply(): UInt = apply(Width())
+  /** Create a UInt port with specified width. */
+  def apply(width: Width): UInt = new UInt(width)
+  /** Create a UInt with a specified width - compatibility with Chisel2. */
+  def width(width: Int): UInt = apply(Width(width))
+  /** Create a UInt port with specified width. */
+  def width(width: Width): UInt = new UInt(width)
   /** Create a UInt literal with fixed width. */
-  def apply(value: BigInt, width: Int): UInt = apply(value, Width(width))
+  def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
   /** Create a UInt literal with inferred width. */
-  def apply(n: String): UInt = apply(parse(n), parsedWidth(n))
-  /** Create a UInt literal with fixed width. */
-  def apply(n: String, width: Int): UInt = apply(parse(n), width)
-
-  /** Create a UInt type with specified width. */
-  def apply(width: Width): UInt = apply(NO_DIR, width)
-  /** Create a UInt port with specified width. */
-  def apply(dir: Direction, width: Width): UInt = new UInt(dir, width)
+  def apply(n: String): UInt = Lit(n)
+   /** Create a UInt literal with fixed width. */
+  def apply(n: String, width: Int): UInt = Lit(parse(n), width)
   /** Create a UInt literal with specified width. */
-  def apply(value: BigInt, width: Width): UInt = {
+  def apply(value: BigInt, width: Width): UInt = Lit(value, width)
+  def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+   /** Create a UInt literal with inferred width. */
+  def Lit(value: BigInt): UInt = Lit(value, Width())
+  def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n))
+   /** Create a UInt literal with fixed width. */
+  def Lit(n: String, width: Int): UInt = Lit(parse(n), width)
+   /** Create a UInt literal with specified width. */
+  def Lit(value: BigInt, width: Width): UInt = {
     val lit = ULit(value, width)
-    new UInt(NO_DIR, lit.width, Some(lit))
+    val result = new UInt(lit.width, Some(lit))
+    // Bind result to being an Literal
+    result.binding = LitBinding()
+    result
+  }
+
+  /** Create a UInt with a specified width - compatibility with Chisel2. */
+  def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+  /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
+  def apply(value: BigInt): UInt = apply(value, Width())
+  /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+  def apply(dir: Direction, width: Int): UInt = {
+    val result = apply(Width(width))
+    dir match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
   }
 
   private def parse(n: String) = {
@@ -524,17 +574,13 @@ private[core] sealed trait UIntFactory {
 
 object UInt extends UIntFactory
 
-sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = None)
-    extends Bits(dir, width, lit) with Num[SInt] {
+sealed class SInt private (width: Width, lit: Option[SLit] = None)
+    extends Bits(width, lit) with Num[SInt] {
+
   private[core] override def cloneTypeWidth(w: Width): this.type =
-    new SInt(dir, w).asInstanceOf[this.type]
+    new SInt(w).asInstanceOf[this.type]
   private[chisel3] def toType = s"SInt$width"
 
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: SInt => this connect that
-    case _ => this badConnect that
-  }
-
   override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
     SInt(value, width).asInstanceOf[this.type]
 
@@ -630,25 +676,43 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
 
 object SInt {
   /** Create an SInt type with inferred width. */
-  def apply(): SInt = apply(NO_DIR, Width())
-  /** Create an SInt type or port with fixed width. */
-  def apply(dir: Direction = NO_DIR, width: Int): SInt = apply(dir, Width(width))
-  /** Create an SInt port with inferred width. */
-  def apply(dir: Direction): SInt = apply(dir, Width())
+  def apply(): SInt = apply(Width())
+  /** Create a SInt type or port with fixed width. */
+  def apply(width: Width): SInt = new SInt(width)
+  /** Create a SInt type or port with fixed width. */
+  def width(width: Int): SInt = apply(Width(width))
+  /** Create an SInt type with specified width. */
+  def width(width: Width): SInt = new SInt(width)
 
   /** Create an SInt literal with inferred width. */
-  def apply(value: BigInt): SInt = apply(value, Width())
+  def apply(value: BigInt): SInt = Lit(value)
   /** Create an SInt literal with fixed width. */
-  def apply(value: BigInt, width: Int): SInt = apply(value, Width(width))
+  def apply(value: BigInt, width: Int): SInt = Lit(value, width)
 
-  /** Create an SInt type with specified width. */
-  def apply(width: Width): SInt = new SInt(NO_DIR, width)
-  /** Create an SInt port with specified width. */
-  def apply(dir: Direction, width: Width): SInt = new SInt(dir, width)
   /** Create an SInt literal with specified width. */
-  def apply(value: BigInt, width: Width): SInt = {
+  def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+
+  def Lit(value: BigInt): SInt = Lit(value, Width())
+  def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
+   /** Create an SInt literal with specified width. */
+  def Lit(value: BigInt, width: Width): SInt = {
+
     val lit = SLit(value, width)
-    new SInt(NO_DIR, lit.width, Some(lit))
+    val result = new SInt(lit.width, Some(lit))
+    // Bind result to being an Literal
+    result.binding = LitBinding()
+    result
+  }
+  /** Create a SInt with a specified width - compatibility with Chisel2. */
+  def apply(dir: Option[Direction] = None, width: Int): SInt = apply(Width(width))
+  /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
+  def apply(dir: Direction, width: Int): SInt = {
+    val result = apply(Width(width))
+    dir match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
   }
 }
 
@@ -656,10 +720,10 @@ object SInt {
 // operations on a Bool make sense?
 /** A data type for booleans, defined as a single bit indicating true or false.
   */
-sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Width(1), lit) {
+sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) {
   private[core] override def cloneTypeWidth(w: Width): this.type = {
     require(!w.known || w.get == 1)
-    new Bool(dir).asInstanceOf[this.type]
+    new Bool().asInstanceOf[this.type]
   }
 
   override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = {
@@ -700,11 +764,26 @@ sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Wi
 object Bool {
   /** Creates an empty Bool.
    */
-  def apply(dir: Direction = NO_DIR): Bool = new Bool(dir)
+  def apply(): Bool = new Bool()
 
   /** Creates Bool literal.
    */
-  def apply(x: Boolean): Bool = new Bool(NO_DIR, Some(ULit(if (x) 1 else 0, Width(1))))
+  def apply(x: Boolean): Bool = Lit(x)
+  def Lit(x: Boolean): Bool = {
+    val result = new Bool(Some(ULit(if (x) 1 else 0, Width(1))))
+    // Bind result to being an Literal
+    result.binding = LitBinding()
+    result
+  }
+  /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+  def apply(dir: Direction): Bool = {
+    val result = apply()
+    dir match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
+  }
 }
 
 object Mux {
@@ -733,6 +812,9 @@ object Mux {
 
   private def doMux[T <: Data](cond: Bool, con: T, alt: T)(implicit sourceInfo: SourceInfo): T = {
     require(con.getClass == alt.getClass, s"can't Mux between ${con.getClass} and ${alt.getClass}")
+    Binding.checkSynthesizable(cond, s"'cond' ($cond)")
+    Binding.checkSynthesizable(con, s"'con' ($con)")
+    Binding.checkSynthesizable(alt, s"'alt' ($alt)")
     val d = alt.cloneTypeWidth(con.width max alt.width)
     pushOp(DefPrim(sourceInfo, d, MultiplexOp, cond.ref, con.ref, alt.ref))
   }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 8826af51..cb6d427d 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -13,13 +13,102 @@ sealed abstract class Direction(name: String) {
   override def toString: String = name
   def flip: Direction
 }
-object INPUT  extends Direction("input") { override def flip: Direction = OUTPUT }
-object OUTPUT extends Direction("output") { override def flip: Direction = INPUT }
-object NO_DIR extends Direction("?") { override def flip: Direction = NO_DIR }
+object Direction {
+  object Input  extends Direction("input") { override def flip: Direction = Output }
+  object Output extends Direction("output") { override def flip: Direction = Input }
+  object Unspecified extends Direction("unspecified") { override def flip: Direction = Input }
+}
+
+@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
+object debug {  // scalastyle:ignore object.name
+  def apply (arg: Data): Data = arg
+}
+
+object DataMirror {
+  def widthOf(target: Data): Width = target.width
+}
+
+/**
+* Input, Output, and Flipped are used to define the directions of Module IOs.
+*
+* Note that they do not currently call target to be a newType or cloneType.
+* This is nominally for performance reasons to avoid too many extra copies when
+* something is flipped multiple times.
+*
+* Thus, an error will be thrown if these are used on bound Data
+*/
+object Input {
+  def apply[T<:Data](target: T): T = {
+    Data.setFirrtlDirection(target, Direction.Input)
+    Binding.bind(target, InputBinder, "Error: Cannot set as input ")
+  }
+}
+object Output {
+  def apply[T<:Data](target: T): T = {
+    Data.setFirrtlDirection(target, Direction.Output)
+    Binding.bind(target, OutputBinder, "Error: Cannot set as output ")
+  }
+}
+object Flipped {
+  def apply[T<:Data](target: T): T = {
+    Data.setFirrtlDirection(target, Data.getFirrtlDirection(target).flip)
+    Binding.bind(target, FlippedBinder, "Error: Cannot flip ")
+  }
+}
+
+object Data {
+  /**
+  * This function returns true if the FIRRTL type of this Data should be flipped
+  * relative to other nodes.
+  *
+  * Note that the current scheme only applies Flip to Elements or Vec chains of
+  * Elements.
+  *
+  * A Bundle is never marked flip, instead preferring its root fields to be marked
+  *
+  * The Vec check is due to the fact that flip must be factored out of the vec, ie:
+  * must have flip field: Vec(UInt) instead of field: Vec(flip UInt)
+  */
+  private[chisel3] def isFlipped(target: Data): Boolean = target match {
+    case (element: Element) => element.binding.direction == Some(Direction.Input)
+    case (vec: Vec[Data @unchecked]) => isFlipped(vec.sample_element)
+    case (bundle: Bundle) => false
+  }
+
+  /** This function returns the "firrtl" flipped-ness for the specified object.
+    *
+    * @param target the object for which we want the "firrtl" flipped-ness.
+    */
+  private[chisel3] def isFirrtlFlipped(target: Data): Boolean = {
+    Data.getFirrtlDirection(target) == Direction.Input
+  }
+
+  /** This function gets the "firrtl" direction for the specified object.
+    *
+    * @param target the object for which we want to get the "firrtl" direction.
+    */
+  private[chisel3] def getFirrtlDirection(target: Data): Direction = target match {
+    case (vec: Vec[Data @unchecked]) => vec.sample_element.firrtlDirection
+    case _ => target.firrtlDirection
+  }
+
+  /** This function sets the "firrtl" direction for the specified object.
+    *
+    * @param target the object for which we want to set the "firrtl" direction.
+    */
+  private[chisel3] def setFirrtlDirection(target: Data, direction: Direction): Unit = target match {
+    case (vec: Vec[Data @unchecked]) => vec.sample_element.firrtlDirection = direction
+    case _ => target.firrtlDirection = direction
+  }
 
-/** Mixing in this trait flips the direction of an Aggregate. */
-trait Flipped extends Data {
-  this.overrideDirection(_.flip, !_)
+  implicit class AddDirectionToData[T<:Data](val target: T) extends AnyVal {
+    @deprecated("Input(Data) should be used over Data.asInput", "gchisel")
+    def asInput: T = Input(target)
+    @deprecated("Output(Data) should be used over Data.asOutput", "gchisel")
+    def asOutput: T = Output(target)
+    @deprecated("Flipped(Data) should be used over Data.flip", "gchisel")
+    def flip(): T = Flipped(target)
+  }
 }
 
 /** This forms the root of the type system for wire data types. The data value
@@ -27,42 +116,56 @@ trait Flipped extends Data {
   * time) of bits, and must have methods to pack / unpack structured data to /
   * from bits.
   */
-abstract class Data(dirArg: Direction) extends HasId {
-  def dir: Direction = dirVar
-
-  // Sucks this is mutable state, but cloneType doesn't take a Direction arg
-  private var isFlipVar = dirArg == INPUT
-  private var dirVar = dirArg
-  private[core] def isFlip = isFlipVar
-
-  private[core] def overrideDirection(newDir: Direction => Direction,
-                                        newFlip: Boolean => Boolean): this.type = {
-    this.isFlipVar = newFlip(this.isFlipVar)
-    for (field <- this.flatten)
-      (field: Data).dirVar = newDir((field: Data).dirVar)
-    this
-  }
-  def asInput: this.type = cloneType.overrideDirection(_ => INPUT, _ => true)
-  def asOutput: this.type = cloneType.overrideDirection(_ => OUTPUT, _ => false)
-  def flip(): this.type = cloneType.overrideDirection(_.flip, !_)
+abstract class Data extends HasId {
+  // Return ALL elements at root of this type.
+  // Contasts with flatten, which returns just Bits
+  private[chisel3] def allElements: Seq[Element]
 
   private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     throwException(s"cannot connect ${this} and ${that}")
-  private[core] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
-    pushCommand(Connect(sourceInfo, this.lref, that.ref))
-  private[core] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
-    pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
-  private[core] def lref: Node = Node(this)
+  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
+    Binding.checkSynthesizable(that, s"'that' ($that)")
+    try {
+      MonoConnect.connect(sourceInfo, this, that, Builder.forcedModule)
+    } catch {
+      case MonoConnect.MonoConnectException(message) =>
+        throwException(
+          s"Connection between sink ($this) and source ($that) failed @$message"
+        )
+    }
+  }
+  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
+    Binding.checkSynthesizable(that, s"'that' ($that)")
+    try {
+      BiConnect.connect(sourceInfo, this, that, Builder.forcedModule)
+    } catch {
+      case BiConnect.BiConnectException(message) =>
+        throwException(
+          s"Connection between left ($this) and source ($that) failed @$message"
+        )
+    }
+  }
+  private[chisel3] def lref: Node = Node(this)
   private[chisel3] def ref: Arg = if (isLit) litArg.get else lref
   private[core] def cloneTypeWidth(width: Width): this.type
   private[chisel3] def toType: String
   private[core] def width: Width
 
-  def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
-
-  def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
-
   def cloneType: this.type
+  def chiselCloneType: this.type = {
+    // Call the user-supplied cloneType method
+    val clone = this.cloneType
+    Data.setFirrtlDirection(clone, Data.getFirrtlDirection(this))
+    //TODO(twigg): Do recursively for better error messages
+    for((clone_elem, source_elem) <- clone.allElements zip this.allElements) {
+      clone_elem.binding = UnboundBinding(source_elem.binding.direction)
+    }
+    clone
+  }
+  final def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this connect that
+  final def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this bulkConnect that
   def litArg(): Option[LitArg] = None
   def litValue(): BigInt = litArg.get.num
   def isLit(): Boolean = litArg.isDefined
@@ -100,7 +203,7 @@ abstract class Data(dirArg: Direction) extends HasId {
 
   def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = {
     var i = 0
-    val wire = Wire(this.cloneType)
+    val wire = Wire(this.chiselCloneType)
     val bits =
       if (that.width.known && that.width.get >= wire.width.get) {
         that
@@ -132,6 +235,10 @@ abstract class Data(dirArg: Direction) extends HasId {
 
   def do_asUInt(implicit sourceInfo: SourceInfo): UInt =
     SeqUtils.do_asUInt(this.flatten)(sourceInfo)
+
+  // firrtlDirection is the direction we report to firrtl.
+  // It maintains the user-specified value (as opposed to the "actual" or applied/propagated value).
+  var firrtlDirection: Direction = Direction.Unspecified
 }
 
 object Wire {
@@ -147,9 +254,14 @@ object Wire {
 
   def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = {
     val x = Reg.makeType(t, null.asInstanceOf[T], init)
+
+    // Bind each element of x to being a Wire
+    Binding.bind(x, WireBinder(Builder.forcedModule), "Error: t")
+
     pushCommand(DefWire(sourceInfo, x))
     pushCommand(DefInvalid(sourceInfo, x.ref))
     if (init != null) {
+      Binding.checkSynthesizable(init, s"'init' ($init)")
       x := init
     }
     x
@@ -157,18 +269,26 @@ object Wire {
 }
 
 object Clock {
-  def apply(dir: Direction = NO_DIR): Clock = new Clock(dir)
+  def apply(): Clock = new Clock
+  def apply(dir: Direction): Clock = {
+    val result = apply()
+    dir match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
+  }
 }
 
 // TODO: Document this.
-sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
-  def cloneType: this.type = Clock(dirArg).asInstanceOf[this.type]
+sealed class Clock extends Element(Width(1)) {
+  def cloneType: this.type = Clock().asInstanceOf[this.type]
   private[chisel3] override def flatten: IndexedSeq[Bits] = IndexedSeq()
   private[core] def cloneTypeWidth(width: Width): this.type = cloneType
   private[chisel3] def toType = "Clock"
 
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: Clock => this connect that
-    case _ => this badConnect that
+  override def connect (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
+    case _: Clock => super.connect(that)(sourceInfo)
+    case _ => super.badConnect(that)(sourceInfo)
   }
 }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index 38f5ef14..931a0489 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -19,9 +19,11 @@ object Mem {
     * @param t data type of memory element
     */
   def apply[T <: Data](size: Int, t: T): Mem[T] = macro MemTransform.apply[T]
-
   def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo): Mem[T] = {
-    val mt  = t.cloneType
+    val mt  = t.chiselCloneType
+    Binding.bind(mt, NoDirectionBinder, "Error: fresh t")
+    // TODO(twigg): Remove need for this Binding
+
     val mem = new Mem(mt, size)
     pushCommand(DefMemory(sourceInfo, mem, mt, size)) // TODO multi-clock
     mem
@@ -60,7 +62,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
     *
     * @param idx memory element index to write into
     * @param data new data to write
-    * @param mask write mask as a Vec of Bool: a write to the Vec element in
+    * @param mask write mask as a Seq of Bool: a write to the Vec element in
     * memory is only performed if the corresponding mask index is true.
     *
     * @note this is only allowed if the memory's element data type is a Vec
@@ -79,9 +81,17 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
       when (cond) { port := datum }
   }
 
-  private def makePort(sourceInfo: SourceInfo, idx: UInt, dir: MemPortDirection): T =
-    pushCommand(DefMemPort(sourceInfo,
-        t.cloneType, Node(this), dir, idx.ref, Node(idx._parent.get.clock))).id
+  private def makePort(sourceInfo: SourceInfo, idx: UInt, dir: MemPortDirection): T = {
+    Binding.checkSynthesizable(idx, s"'idx' ($idx)")
+
+    val port = pushCommand(
+      DefMemPort(sourceInfo,
+       t.chiselCloneType, Node(this), dir, idx.ref, Node(idx._parent.get.clock))
+    ).id
+    // Bind each element of port to being a MemoryPort
+    Binding.bind(port, MemoryPortBinder(Builder.forcedModule), "Error: Fresh t")
+    port
+  }
 }
 
 /** A combinational-read, sequential-write memory.
@@ -107,7 +117,10 @@ object SeqMem {
   def apply[T <: Data](size: Int, t: T): SeqMem[T] = macro MemTransform.apply[T]
 
   def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo): SeqMem[T] = {
-    val mt  = t.cloneType
+    val mt  = t.chiselCloneType
+    Binding.bind(mt, NoDirectionBinder, "Error: fresh t")
+    // TODO(twigg): Remove need for this Binding
+
     val mem = new SeqMem(mt, size)
     pushCommand(DefSeqMemory(sourceInfo, mem, mt, size)) // TODO multi-clock
     mem
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 5af744c4..450f5b58 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -4,12 +4,11 @@ package chisel3.core
 
 import scala.collection.mutable.ArrayBuffer
 import scala.language.experimental.macros
-
 import chisel3.internal._
-import chisel3.internal.Builder.pushCommand
-import chisel3.internal.Builder.dynamicContext
+import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
-import chisel3.internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
+import chisel3.internal.firrtl.{Command => _, _}
+import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -26,14 +25,19 @@ object Module {
     // module de-duplication in FIRRTL emission.
     val childSourceInfo = UnlocatableSourceInfo
 
-    val parent = dynamicContext.currentModule
-    val m = bc.setRefs()
+    val parent: Option[Module] = Builder.currentModule
+    val m = bc.setRefs() // This will set currentModule!
     m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs
-    dynamicContext.currentModule = parent
+    Builder.currentModule = parent // Back to parent!
     val ports = m.computePorts
     Builder.components += Component(m, m.name, ports, m._commands)
-    pushCommand(DefInstance(sourceInfo, m, ports))
-    m.setupInParent(childSourceInfo)
+    // Avoid referencing 'parent' in top module
+    if(!Builder.currentModule.isEmpty) {
+      pushCommand(DefInstance(sourceInfo, m, ports))
+      m.setupInParent(childSourceInfo)
+    }
+
+    m
   }
 }
 
@@ -52,10 +56,41 @@ extends HasId {
   def this(_reset: Bool)  = this(None, Option(_reset))
   def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
 
+  // This function binds the iodef as a port in the hardware graph
+  private[chisel3] def Port[T<:Data](iodef: T): iodef.type = {
+    // Bind each element of the iodef to being a Port
+    Binding.bind(iodef, PortBinder(this), "Error: iodef")
+    iodef
+  }
+
+  private[core] var ioDefined: Boolean = false
+
+  /**
+   * This must wrap the datatype used to set the io field of any Module.
+   * i.e. All concrete modules must have defined io in this form:
+   * [lazy] val io[: io type] = IO(...[: io type])
+   *
+   * Items in [] are optional.
+   *
+   * The granted iodef WILL NOT be cloned (to allow for more seamless use of
+   * anonymous Bundles in the IO) and thus CANNOT have been bound to any logic.
+   * This will error if any node is bound (e.g. due to logic in a Bundle
+   * constructor, which is considered improper).
+   *
+   * TODO(twigg): Specifically walk the Data definition to call out which nodes
+   * are problematic.
+   */
+  def IO[T<:Data](iodef: T): iodef.type = {
+    require(!ioDefined, "Another IO definition for this module was already declared!")
+    ioDefined = true
+
+    Port(iodef)
+  }
+
   private[core] val _namespace = Builder.globalNamespace.child
   private[chisel3] val _commands = ArrayBuffer[Command]()
   private[core] val _ids = ArrayBuffer[HasId]()
-  dynamicContext.currentModule = Some(this)
+  Builder.currentModule = Some(this)
 
   /** Desired name of this module. */
   def desiredName = this.getClass.getName.split('.').last
@@ -67,8 +102,8 @@ extends HasId {
     * connections in and out of a Module may only go through `io` elements.
     */
   def io: Bundle
-  val clock = Clock(INPUT)
-  val reset = Bool(INPUT)
+  val clock = Port(Input(Clock()))
+  val reset = Port(Input(Bool()))
 
   private[chisel3] def addId(d: HasId) { _ids += d }
 
@@ -76,10 +111,17 @@ extends HasId {
     ("clk", clock), ("reset", reset), ("io", io)
   )
 
-  private[core] def computePorts = for((name, port) <- ports) yield {
-    val bundleDir = if (port.isFlip) INPUT else OUTPUT
-    Port(port, if (port.dir == NO_DIR) bundleDir else port.dir)
-  }
+  private[core] def computePorts: Seq[firrtl.Port] =
+    for((name, port) <- ports) yield {
+      // If we're auto-wrapping IO definitions, do so now.
+      if (compileOptions.autoIOWrap && name == "io" && !ioDefined) {
+        IO(port)
+      }
+      // Port definitions need to know input or output at top-level.
+      // By FIRRTL semantics, 'flipped' becomes an Input
+      val direction = if(Data.isFlipped(port)) Direction.Input else Direction.Output
+      firrtl.Port(port, direction)
+    }
 
   private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
     _parent match {
@@ -141,4 +183,6 @@ extends HasId {
     _ids.foreach(_._onModuleClose)
     this
   }
+  // For debuggers/testers
+  lazy val getPorts = computePorts
 }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
new file mode 100644
index 00000000..4ba921fa
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
@@ -0,0 +1,177 @@
+package chisel3.core
+
+import chisel3.internal.Builder.{compileOptions, pushCommand}
+import chisel3.internal.firrtl.Connect
+import scala.language.experimental.macros
+import chisel3.internal.sourceinfo.{DeprecatedSourceInfo, SourceInfo, SourceInfoTransform, UnlocatableSourceInfo, WireTransform}
+
+/**
+* MonoConnect.connect executes a mono-directional connection element-wise.
+*
+* Note that this isn't commutative. There is an explicit source and sink
+* already determined before this function is called.
+*
+* The connect operation will recurse down the left Data (with the right Data).
+* An exception will be thrown if a movement through the left cannot be matched
+* in the right. The right side is allowed to have extra Bundle fields.
+* Vecs must still be exactly the same size.
+*
+* See elemConnect for details on how the root connections are issued.
+*
+* Note that a valid sink must be writable so, one of these must hold:
+* - Is an internal writable node (Reg or Wire)
+* - Is an output of the current module
+* - Is an input of a submodule of the current module
+*
+* Note that a valid source must be readable so, one of these must hold:
+* - Is an internal readable node (Reg, Wire, Op)
+* - Is a literal
+* - Is a port of the current module or submodule of the current module
+*/
+
+object MonoConnect {
+  // These are all the possible exceptions that can be thrown.
+  case class MonoConnectException(message: String) extends Exception(message)
+  // These are from element-level connection
+  def UnreadableSourceException =
+    MonoConnectException(": Source is unreadable from current module.")
+  def UnwritableSinkException =
+    MonoConnectException(": Sink is unwriteable by current module.")
+  def UnknownRelationException =
+    MonoConnectException(": Sink or source unavailable to current module.")
+  // These are when recursing down aggregate types
+  def MismatchedVecException =
+    MonoConnectException(": Sink and Source are different length Vecs.")
+  def MissingFieldException(field: String) =
+    MonoConnectException(s": Source Bundle missing field ($field).")
+  def MismatchedException(sink: String, source: String) =
+    MonoConnectException(s": Sink ($sink) and Source ($source) have different types.")
+
+  /** This function is what recursively tries to connect a sink and source together
+  *
+  * There is some cleverness in the use of internal try-catch to catch exceptions
+  * during the recursive decent and then rethrow them with extra information added.
+  * This gives the user a 'path' to where in the connections things went wrong.
+  */
+  def connect(sourceInfo: SourceInfo, sink: Data, source: Data, context_mod: Module): Unit =
+    (sink, source) match {
+      // Handle element case (root case)
+      case (sink_e: Element, source_e: Element) => {
+        elemConnect(sourceInfo, sink_e, source_e, context_mod)
+        // TODO(twigg): Verify the element-level classes are connectable
+      }
+      // Handle Vec case
+      case (sink_v: Vec[Data @unchecked], source_v: Vec[Data @unchecked]) => {
+        if(sink_v.length != source_v.length) { throw MismatchedVecException }
+        for(idx <- 0 until sink_v.length) {
+          try {
+            connect(sourceInfo, sink_v(idx), source_v(idx), context_mod)
+          } catch {
+            case MonoConnectException(message) => throw MonoConnectException(s"($idx)$message")
+          }
+        }
+      }
+      // Handle Bundle case
+      case (sink_b: Bundle, source_b: Bundle) => {
+        // For each field, descend with right
+        for((field, sink_sub) <- sink_b.elements) {
+          try {
+            source_b.elements.get(field) match {
+              case Some(source_sub) => connect(sourceInfo, sink_sub, source_sub, context_mod)
+              case None => {
+                if (compileOptions.connectFieldsMustMatch) {
+                  throw MissingFieldException(field)
+                }
+              }
+            }
+          } catch {
+            case MonoConnectException(message) => throw MonoConnectException(s".$field$message")
+          }
+        }
+      }
+      // Sink and source are different subtypes of data so fail
+      case (sink, source) => throw MismatchedException(sink.toString, source.toString)
+    }
+
+  // This function (finally) issues the connection operation
+  private def issueConnect(sink: Element, source: Element)(implicit sourceInfo: SourceInfo): Unit = {
+    pushCommand(Connect(sourceInfo, sink.lref, source.ref))
+  }
+
+  // This function checks if element-level connection operation allowed.
+  // Then it either issues it or throws the appropriate exception.
+  def elemConnect(implicit sourceInfo: SourceInfo, sink: Element, source: Element, context_mod: Module): Unit = {
+    import Direction.{Input, Output} // Using extensively so import these
+    // If source has no location, assume in context module
+    // This can occur if is a literal, unbound will error previously
+    val sink_mod: Module   = sink.binding.location.getOrElse(throw UnwritableSinkException)
+    val source_mod: Module = source.binding.location.getOrElse(context_mod)
+
+    val sink_direction: Option[Direction] = sink.binding.direction
+    val source_direction: Option[Direction] = source.binding.direction
+    // None means internal
+
+    // CASE: Context is same module that both left node and right node are in
+    if( (context_mod == sink_mod) && (context_mod == source_mod) ) {
+      (sink_direction, source_direction) match {
+        //    SINK          SOURCE
+        //    CURRENT MOD   CURRENT MOD
+        case (Some(Output), _) => issueConnect(sink, source)
+        case (None,         _) => issueConnect(sink, source)
+        case (Some(Input),  _) => throw UnwritableSinkException
+      }
+    }
+
+    // CASE: Context is same module as sink node and right node is in a child module
+    else if( (sink_mod == context_mod) &&
+             (source_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, right node better be a port node and thus have a direction
+      (sink_direction, source_direction) match {
+        //    SINK          SOURCE
+        //    CURRENT MOD   CHILD MOD
+        case (None,         Some(Output)) => issueConnect(sink, source)
+        case (None,         Some(Input))  => issueConnect(sink, source)
+        case (Some(Output), Some(Output)) => issueConnect(sink, source)
+        case (Some(Output), Some(Input))  => issueConnect(sink, source)
+        case (_,            None) => throw UnreadableSourceException
+        case (Some(Input),  Some(Output)) if (compileOptions.tryConnectionsSwapped) => issueConnect(source, sink)
+        case (Some(Input),  _)    => throw UnwritableSinkException
+      }
+    }
+
+    // CASE: Context is same module as source node and sink node is in child module
+    else if( (source_mod == context_mod) &&
+             (sink_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, left node better be a port node and thus have a direction
+      (sink_direction, source_direction) match {
+        //    SINK          SOURCE
+        //    CHILD MOD     CURRENT MOD
+        case (Some(Input),  _) => issueConnect(sink, source)
+        case (Some(Output), _) => throw UnwritableSinkException
+        case (None,         _) => throw UnwritableSinkException
+      }
+    }
+
+    // CASE: Context is the parent module of both the module containing sink node
+    //                                        and the module containing source node
+    //   Note: This includes case when sink and source in same module but in parent
+    else if( (sink_mod._parent.map(_ == context_mod).getOrElse(false)) &&
+             (source_mod._parent.map(_ == context_mod).getOrElse(false))
+    ) {
+      // Thus both nodes must be ports and have a direction
+      (sink_direction, source_direction) match {
+        //    SINK          SOURCE
+        //    CHILD MOD     CHILD MOD
+        case (Some(Input),  Some(Input))  => issueConnect(sink, source)
+        case (Some(Input),  Some(Output)) => issueConnect(sink, source)
+        case (Some(Output), _)            => throw UnwritableSinkException
+        case (_,            None)         => throw UnreadableSourceException
+        case (None,         _)            => throw UnwritableSinkException
+      }
+    }
+
+    // Not quite sure where left and right are compared to current module
+    // so just error out
+    else throw UnknownRelationException
+  }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
index b0a3c955..400c144d 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
@@ -24,13 +24,13 @@ object printf { // scalastyle:ignore object.name
     * @param data format string varargs containing data to print
     */
   def apply(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
-    when (!(Builder.dynamicContext.currentModule.get.reset)) {
+    when (!Builder.forcedModule.reset) {
       printfWithoutReset(fmt, data:_*)
     }
   }
 
   private[core] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
-    val clock = Builder.dynamicContext.currentModule.get.clock
+    val clock = Builder.forcedModule.clock
     pushCommand(Printf(sourceInfo, Node(clock), fmt, data.map((d: Bits) => d.ref)))
   }
 }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index b0dd3bb1..6c357461 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -10,13 +10,16 @@ import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
 object Reg {
   private[core] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = {
     if (t ne null) {
-      t.cloneType
+      if (Builder.compileOptions.regTypeMustBeUnbound) {
+        Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using cloneType?")
+      }
+      t.chiselCloneType
     } else if (next ne null) {
       next.cloneTypeWidth(Width())
     } else if (init ne null) {
       init.litArg match {
         // For e.g. Reg(init=UInt(0, k)), fix the Reg's width to k
-        case Some(lit) if lit.forcedWidth => init.cloneType
+        case Some(lit) if lit.forcedWidth => init.chiselCloneType
         case _ => init.cloneTypeWidth(Width())
       }
     } else {
@@ -58,12 +61,18 @@ object Reg {
     // system improves, this may be changed.
     val x = makeType(t, next, init)
     val clock = Node(x._parent.get.clock) // TODO multi-clock
+
+    // Bind each element of x to being a Reg
+    Binding.bind(x, RegBinder(Builder.forcedModule), "Error: t")
+
     if (init == null) {
       pushCommand(DefReg(sourceInfo, x, clock))
     } else {
+      Binding.checkSynthesizable(init, s"'init' ($init)")
       pushCommand(DefRegInit(sourceInfo, x, clock, Node(x._parent.get.reset), init.ref))
     }
     if (next != null) {
+      Binding.checkSynthesizable(next, s"'next' ($next)")
       x := next
     }
     x
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index cecbd91e..9f2b1631 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -56,11 +56,11 @@ private[chisel3] class IdGen {
 }
 
 private[chisel3] trait HasId {
-  private[chisel3] def _onModuleClose {} // scalastyle:ignore method.name
-  private[chisel3] val _parent = Builder.dynamicContext.currentModule
+  private[chisel3] def _onModuleClose: Unit = {} // scalastyle:ignore method.name
+  private[chisel3] val _parent: Option[Module] = Builder.currentModule
   _parent.foreach(_.addId(this))
 
-  private[chisel3] val _id = Builder.idGen.next
+  private[chisel3] val _id: Long = Builder.idGen.next
   override def hashCode: Int = _id.toInt
   override def equals(that: Any): Boolean = that match {
     case x: HasId => _id == x._id
@@ -97,35 +97,58 @@ private[chisel3] trait HasId {
   private[chisel3] def getRef: Arg = _ref.get
 }
 
-private[chisel3] class DynamicContext {
+private[chisel3] class DynamicContext(optionMap: Option[Map[String, String]] = None) {
   val idGen = new IdGen
   val globalNamespace = new Namespace(None, Set())
   val components = ArrayBuffer[Component]()
   var currentModule: Option[Module] = None
   val errors = new ErrorLog
+  val compileOptions = new CompileOptions(optionMap match {
+    case Some(map: Map[String, String]) => map
+    case None => Map[String, String]()
+  })
 }
 
 private[chisel3] object Builder {
   // All global mutable state must be referenced via dynamicContextVar!!
   private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None)
+  private def dynamicContext: DynamicContext =
+    dynamicContextVar.value.getOrElse(new DynamicContext)
 
-  def dynamicContext: DynamicContext =
-    dynamicContextVar.value getOrElse (new DynamicContext)
   def idGen: IdGen = dynamicContext.idGen
   def globalNamespace: Namespace = dynamicContext.globalNamespace
   def components: ArrayBuffer[Component] = dynamicContext.components
+  def compileOptions = dynamicContext.compileOptions
 
+  def currentModule: Option[Module] = dynamicContext.currentModule
+  def currentModule_=(target: Option[Module]): Unit = {
+    dynamicContext.currentModule = target
+  }
+  def forcedModule: Module = currentModule match {
+    case Some(module) => module
+    case None => throw new Exception(
+      "Error: Not in a Module. Likely cause: Missed Module() wrap or bare chisel API call."
+      // A bare api call is, e.g. calling Wire() from the scala console).
+    )
+  }
+
+  // TODO(twigg): Ideally, binding checks and new bindings would all occur here
+  // However, rest of frontend can't support this yet.
   def pushCommand[T <: Command](c: T): T = {
-    dynamicContext.currentModule.foreach(_._commands += c)
+    forcedModule._commands += c
     c
   }
-  def pushOp[T <: Data](cmd: DefPrim[T]): T = pushCommand(cmd).id
+  def pushOp[T <: Data](cmd: DefPrim[T]): T = {
+    // Bind each element of the returned Data to being a Op
+    Binding.bind(cmd.id, OpBinder(forcedModule), "Error: During op creation, fresh result")
+    pushCommand(cmd).id
+  }
 
   def errors: ErrorLog = dynamicContext.errors
   def error(m: => String): Unit = errors.error(m)
 
-  def build[T <: Module](f: => T): Circuit = {
-    dynamicContextVar.withValue(Some(new DynamicContext)) {
+  def build[T <: Module](f: => T, optionMap: Option[Map[String, String]] = None): Circuit = {
+    dynamicContextVar.withValue(Some(new DynamicContext(optionMap))) {
       errors.info("Elaborating design...")
       val mod = f
       mod.forceName(mod.name, globalNamespace)
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
new file mode 100644
index 00000000..e040201b
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
@@ -0,0 +1,22 @@
+// See LICENSE for license details.
+
+package chisel3.internal
+
+/** Initialize compilation options from a string map.
+  *
+  * @param optionsMap the map from "option" to "value"
+  */
+class CompileOptions(optionsMap: Map[String, String]) {
+  // The default for settings related to "strictness".
+  val strictDefault: String = optionsMap.getOrElse("strict", "false")
+  val looseDefault: String = (!(strictDefault.toBoolean)).toString
+  // Should Bundle connections require a strict match of fields.
+  // If true and the same fields aren't present in both source and sink, a MissingFieldException,
+  // MissingLeftFieldException, or MissingRightFieldException will be thrown.
+  val connectFieldsMustMatch: Boolean = optionsMap.getOrElse("connectFieldsMustMatch", strictDefault).toBoolean
+  val regTypeMustBeUnbound: Boolean = optionsMap.getOrElse("regTypeMustBeUnbound", strictDefault).toBoolean
+  val autoIOWrap: Boolean = optionsMap.getOrElse("autoIOWrap", looseDefault).toBoolean
+  val portDeterminesDirection: Boolean = optionsMap.getOrElse("portDeterminesDirection", looseDefault).toBoolean
+  val tryConnectionsSwapped: Boolean = optionsMap.getOrElse("tryConnectionsSwapped", looseDefault).toBoolean
+  val assumeLHSIsOutput: Boolean = optionsMap.getOrElse("assumeLHSIsOutput", looseDefault).toBoolean
+}