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AgeCommit message (Expand)Author
2017-05-12Changed multiplication of SInt and UInt (#611)Adam Izraelevitz
2017-05-10Add implicit CompileOptions to Record and Bundle (#595)Jack Koenig
2017-05-04Connecting basic types wrong should error in chisel (#497)Chick Markley
2017-05-03Clear clock and reset scope for RawModule (#607)Richard Lin
2017-04-26Deprecate fromBits and clock/reset constructors (#583)Richard Lin
2017-04-26Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)Jim Lawson
2017-04-25Remove explicit import of NotStrict - fixes #492 (#494)Jim Lawson
2017-04-21Remove VecLike/IndexedSeq from Mem type (#589)Richard Lin
2017-04-15 Fix assignment from 0-entry Vec: add test (#580)Andrew Waterman
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-04-12Fix one hot mux (#573)Chick Markley
2017-04-04Use input element to decide if Vec of values has direction (#570)Jack Koenig
2017-04-04Define CompileOptions case class to support CompileOptions manipulation. (#572)Jim Lawson
2017-04-02Make Module instantiations draw clock from Builder instead of parent (#568)Jack Koenig
2017-03-28Creating FixedPoint literals was throwing away width when specifically provided.chick
2017-03-27Support Vec(0) fields in Bundles, just like Option[Data]; add testAndrew Waterman
2017-03-24Fix getWidth on empty Vecs; add testAndrew Waterman
2017-03-24Fixed fix, allow Mux of different binary points and widths (#559)Richard Lin
2017-03-13Revert "Change Vec creation to check if gen is lit (and hence needs t… (#530)Jim Lawson
2017-03-08Deprecate old Reg with nulls constructor (#455)Richard Lin
2017-02-27Record: allow elements to start with a digitWesley W. Terpstra
2017-02-24Fix mismatch between Chisel and Firrtl on UInt -& UIntJack Koenig
2017-02-24Escape % in assertion messagesJack Koenig
2017-02-23Fend off future bug - replace FixedPoint ":=" with "connect". (#516)Jim Lawson
2017-02-22Bugfix #513. Fix BPSet width inference in Chisel3 (#523)Adam Izraelevitz
2017-02-17Builderreflectionfix (#515)Angie Wang
2017-02-16Add scaladoc examples for Vec and Bundle (#511)Chick Markley
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
2017-02-15Blackbox comments spelling correction thanks to edwardcwangFabien Marteau
2017-02-15BlackBox documentation: adding the verilog template to generateFabien Marteau
2017-02-15Adding a BlackBox example in code documentationFabien Marteau
2017-02-15Implement asTypeOf, refactor internal APIs (#450)Richard Lin
2017-02-15Fixed point factory stuff (#505)Chick Markley
2017-02-08Add Analog typeJack Koenig
2017-02-08Add counter for depth of when scopeJack Koenig
2017-02-07Fix up Absolute value #abs (#491)Chick Markley
2017-02-07Add macro for compile options materialize to prevent its use in chisel coreducky
2017-02-07Rename SeqMem to SyncReadMem. (#490)Jim Lawson
2017-02-03Added vec IO tests for #104 (#480)Jim Lawson
2017-02-03Fix potential NPE if we try to evaluate isMissingIOWrapper() inside IO(). (#479)Jim Lawson
2017-01-31Make Module and Bundle properly use empty namespacesJack
2017-01-27Clean names of private vals in Modulesjackkoenig
2017-01-27Have checkpoint report (and clear) non-fatal errors. (#376)Jim Lawson
2017-01-25Better name propagation by macros (#327)Richard Lin
2017-01-20Add Record as new superclass of Bundle (#366)Jack Koenig
2017-01-13Make fromBits work with types other than UInt (#424)grebe
2016-12-22Merge branch 'master' into fixedPointFromBitsgrebe
2016-12-19Merge branch 'master' into exceptionfixJim Lawson
2016-12-13Fix test.Paul Rigge
2016-12-13CheckpointPaul Rigge
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