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Enables changing FIRRTL's IR to only accept multiplication of identical
types.
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Fixes #495
Helps distinguish between Records/Bundles defined in Chisel._ vs.
chisel3._. Also override compilationOptions when bulk connecting
Records/Bundles defined in Chisel._. This allows Records/Bundles defined
in Chisel._ code to be correctly bulk connected in chisel3._ code.
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* Remove explicit import of NotStrict - fixes #492
* Provide macro for MemBase.apply().
* Provide macro for MemBase.apply().
Since a macro cannot override an abstract method, provide a concrete
apply method n VecLike() that we can override with a macro.
* Remove concrete apply() in VecLike.
Since MemBase no longer extends the trait VecLike, we do not require a concrete method to which we can apply a macro to extract the appropriate CompileOptions.
* Add missing implicit compileOptions to do_pad() and do_zext().
The latter caused:
```
[error] /vm/home/jenkins/workspace/rocket-chip_with_chisel3/hardfloat/src/main/scala/MulAddRecFN.scala:205: too many arguments for method do_zext: (implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo)chisel3.core.SInt
[error] val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
```
* Add SourceInfoTransform macros to Vec methods in order to avoid apply() chain issues.
Since utils methods are no longer NotStrict, Pipe objects need access to the client's compile options. There may be more.
* Respond to review comments.
Don't propagate SourceInfo through helper functions.
Replace old usages of CompileOptionsTransform with the now equivalent SourceInfoTransform and redefine CompileOptionsTransform to only deal with CompileOptions.
Just thread CompileOptions (not SourceInfo) through deprecated functions.
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* Remove explicit import of NotStrict - fixes #492
* Provide macro for MemBase.apply().
* Provide macro for MemBase.apply().
Since a macro cannot override an abstract method, provide a concrete
apply method n VecLike() that we can override with a macro.
* Remove concrete apply() in VecLike.
Since MemBase no longer extends the trait VecLike, we do not require a concrete method to which we can apply a macro to extract the appropriate CompileOptions.
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* Partially revert 8e4ddc62db448b613ae327792e72defca4d115d4
It was an incomplete fix for handling Vec(0).
* Fix assignment from 0-entry Vec: add test
375e2b6a0a456c55298d82837d28986de6211ebc introduced a regression for bundles
containing zero-entry Vecs. Until zero-width UInts are supported, the
zero-entry Vecs need to be flattened out before doing asUInt/asTypeOf on
a bundle. Undoing that commit's replacement of Data.flatten with
Aggregate.getElements is the best interim fix.
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* still trying to find right mix
* Making some progress on Mux1H
* Mux1H that works in non-optimzed fashion for FixedPoint, works pretty well in general
Catches some additional problem edge cases
Some tests that illustrate most of this
* Moved in Angie's code for handling FixedPoint case
Cleaned up tests considerably, per @ducky64 review
* Just a bit more cleanup
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Using the sample_element of the created wire is incorrect because Wires have no
direction so the Wire constructed for a Vec of Module IO was constructed
incorrectly. Fixes #569 and resolves #522.
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Make it relatively easy to override a single CompileOption.
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Fixes #567
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This caused one hot muxing problems in dsptools
FixedPoint spec fixed based on error uncovered by this change
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This also allows asUInt/asTypeOf to work properly on those Bundles,
even though zero-width wire support is lacking.
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Use fold(0) instead of reduce to handle the corner case.
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Allow muxing FxP of different widths and BPs
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* Revert "Change Vec creation to check if gen is lit (and hence needs to be declared)"
This reverts commit dc86e7e1734d6abacb739b488df1de231e6b41b2.
This may address #522 - using chiselCloneType (instead of cloneType) to preserve directionality.
* Add missing implicits to Vec.apply() signature.
* Use correct macro (CompileOptionsTransform) for indexWhere.
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This is necessary for user-defined Record-derived types to retain
the same signal name as they would using a Vec.
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Fixes #501. Also added UIntOps test.
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This turned up after updating #494 (Remove explicit import of NotStrict) and adding the missing implicit CompileOptions to ":="'s signature at which point Scala pointed out FixedPoint's ":=" could not override Data's final ":=" with the same signature: the implicit time bomb.
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* Bugfix #513. Needs better test case
* Improved test
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* change builder for bundle reflection fix
* fixed bug -- should be not assignable
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* Add scaladoc examples for Vec and Bundle
* address comments, added @example tag
eliminate extraneous context
* address comments, added @example tag
eliminate extraneous context
* ok, I've wrestled with the javadoc sytnax, the following commit, is my best result so far
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withClockAndReset, withReset, and withClock allow changing the implicit clock and reset.
Module.clock and Module.reset provide access to the current implicit clock and reset.
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* Don't allow analog to analog monoconnect
adjust tests accordingly
* demonstrate bit loss in shift right for fixed point
* cleaned up some stuff.
this does not test clean due to bug in firrtl
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Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
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* Fix up Absolute value #abs
Defines #abs in Num
Implement #abs in UInt
Change #abs in SInt to return an SInt
Change #abs in FixedPoint to return a FixedPoint
Added a couple of tests
Add some scala style suppression to Bits so I can read code in IntelliJ
* Per review
Add tests that abs works for positive values
Added SInt and UInt tests for abs to new underpopulated IntegerMathSpec
Used fixed point literals in fixed points abs definition
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Retain un-deprecated SeqMem in compatibility mode, deprecate in chisel3.
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* Added vec IO tests for #104
* Added Vec test case for Reg of vecs
* Change Vec creation to check if gen is lit (and hence needs to be declared)
Fixes #104
* Fix tests (add IO())), Vec.fill()
* Fix deprecated usage.
* Add Binding IO() NPE fix so tests pass.
* Fix style - use space consistently.
* Fix style - use space consistently.
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Fix default suggested name of Module instances (now based on desired name
rather than actual assigned name).
Remove parent/child relationship from Namespace.
Previously, Module and Bundle namespaces were "children" of the Module
definition namespace. This could lead to collisions that would give unexpected
names for module instances or Bundle elements. In particular, otherwise
identical modules that instantiate other identical modules in such a way that
the instance cannot be named via reflection would not be deduplicated because
the names of the instances would collide with the names of the modules in the
Builder.globalNamespace.
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* Name propagation
* chiselName everywhere at best-effort level
* Better collision handling
* Allow recursing into inner anonymous functions
* Add for loop and anonymous inner function tests
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Record gives uses the power to create collections of heterogenous elements.
Bundle is a special case of Record that uses reflection to populate the
elements of the collection. Bundle also attempts to implement cloneType whereas
users of Record are required to supply one.
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* Make fromBits work with types other than UInt
* Oops, left in a println
* Add test for truncation/expansion
* Fix stuff that broke when FixedPoint fromBits PR was merged.
* Use .BP shorthand added in previous PR
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