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authorFabien Marteau2017-01-03 09:26:46 +0100
committeredwardcwang2017-02-15 15:30:10 -0800
commit6961d5453fee78b6e968de1792ce880c2c751fbf (patch)
treef326f80bba4680be3c40f732256503d2d0ac1799 /chiselFrontend/src
parent375e2b6a0a456c55298d82837d28986de6211ebc (diff)
Adding a BlackBox example in code documentation
Diffstat (limited to 'chiselFrontend/src')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala14
1 files changed, 13 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index 85a57111..fc659ded 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -23,7 +23,19 @@ case class RawParam(value: String) extends Param
*
* @example
* {{{
- * ... to be written once a spec is finalized ...
+ * import chisel3._
+ * import chisel3.experimental._
+ *
+ * // Example with Xilinx differential buffer IBUFDS
+ * class IBUFDS extends BlackBox(Map("DIFF_TERM" -> "TRUE", // Verilog parameters
+ * "IOSTANDARD" -> "DEFAULT"
+ * )) {
+ * val io = IO(new Bundle {
+ * val O = Output(Clock()) // IO names will be the same
+ * val I = Input(Clock()) // (without 'io_' in prefix)
+ * val IB = Input(Clock()) //
+ * })
+ * }
* }}}
* @note The parameters API is experimental and may change
*/