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authorAndrew Waterman2017-03-24 15:09:07 -0700
committerAndrew Waterman2017-03-24 15:48:36 -0700
commite769e5a26f6bd3f87962ad084776c01316ad6fbf (patch)
treec21afbc5e3699d531a9df117e2c8ae9ea3a038da /chiselFrontend/src
parent347bd2f9b23eb8cf67089c314741d571adf82aac (diff)
Fix getWidth on empty Vecs; add test
Use fold(0) instead of reduce to handle the corner case.
Diffstat (limited to 'chiselFrontend/src')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 2bba14ed..d2953aa3 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -19,7 +19,7 @@ sealed abstract class Aggregate extends Data {
*/
def getElements: Seq[Data]
- private[core] def width: Width = getElements.map(_.width).reduce(_ + _)
+ private[core] def width: Width = getElements.map(_.width).foldLeft(0.W)(_ + _)
private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))