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compatibility package object
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Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.
Resolves #289
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Implemented by adding a Boolean to check for alternating invocations of object
Module.apply and the constructor of abstract class Module.
Fixes #192
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Prefix temporary names with underscores so Verilator won't trace them
Use verilator argument "--trace-underscore" if you want to trace these
signals
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defaultCompileOptions is convenient, but it frequently foils the
compatibility layer by providing strict defaults rather than passing
through the user's CompileOptions. This notably manifests for
chiselCloneType, which has different behavior for chisel3 and Chisel.
Ideally, we'd get rid of defaultCompileOptions within chisel3.core
and only supply it to people who import chisel3._ (attn. @ucbjrl).
That would statically prevent further regressions of this nature
within the core.
The change to Vec.truncateIndex seems extraneous, but I chose an
alternate implementation rather than requiring compileOptions in
another place.
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f1507aa7cec86ca8f5de13ddc96fd046370dfe1d triggers a rocket-chip
regression, because Chisel used to not preserve flippedness on
cloneType.
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fix SeqMem's read port creation
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No more need for e.g.
new Bundle {
def foo(dummy: Int): Data
}
as now you can write
new Bundle {
def foo: Data
}
This also removes code duplication with Module.
h/t @sdtwigg
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* FixedPoint number support for chisel3
FixedPoint numbers have a width and a binary position
Either, neither or both maybe inferred.
Firrtl will convert these to SInts during lowering passes
* Fixes based on Jack's comments on PR #328
* Add experimental warning to FixedPoint class and object
* Fixed comment per Adam's comment on PR #328
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this helps firrtl to infer read enable signals
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Generate a better error message for missing IO() wrapper - fix #305
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clone firrtlDirection when cloning - Issue #306
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Give <> and := legacy behavior in compatibility mode
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Static accesses are strictly checked.
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Code that imports Chisel._ shouldn't see them.
Not sure if requireIOWrap is the right condition... or if cyan is a
good choice of color for deprecation warnings.
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@unchecked is better than matching on _ in this case, because we want to
fail on an unexpected case, rather than silently proceed.
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Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports.
NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence).
We should really thread the CompileOptions through the macro system so the client's implicits are used.
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firrtlDirection should only be used for emitting firrtl. Any checks on the actual direction should use the bound Direction `dir`.
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Scaladocs for utils
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Additionally, fix Clock.asUInt (previously, it threw an esoteric exception), and add a simple test of both.
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In the Chisel frontend, the implicit clock is named clock, but in the
generated FIRRTL, it is named clk. There is no reason for this
discrepancy, and yet fixing it is painful, as it will break test harnesses.
Better to take the pain now than later.
Resolves #258.
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This reverts commit 920f6dc168d8e486733666368c7e363065b685ee.
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Printable was using HasId.instanceName to get full names of Chisel nodes.
instanceName uses the parent module of the HasId to get the Component to use in
calling fullName on the underlying Ref. Unfortunately this means that any
reference to a port of a instance will leave off the instance name. Fixing this
required the following:
- Add Component argument to Printable.unpack so that we can call Arg.fullName
directly in the Printable
- Pass the currently emitting module as the Component to Printable.unpack in
the Emitter
- Remove ability to create FullName Printables from Modules since the Module
name is not known until after the printf is already emitted
This commit also updates the PrintableSpec test to check that FullName and
Decimal printing work on ports of instances
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