Merge branch 'master' into tobits-deprecation

25 files changed, 2185 insertions, 689 deletions

diff --git a/chiselFrontend/src/main/scala/Chisel/Data.scala b/chiselFrontend/src/main/scala/Chisel/Data.scala
deleted file mode 100644
index b953df71..00000000
--- a/chiselFrontend/src/main/scala/Chisel/Data.scala
+++ /dev/null
@@ -1,176 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-import scala.language.experimental.macros
-
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
-
-sealed abstract class Direction(name: String) {
-  override def toString: String = name
-  def flip: Direction
-}
-object INPUT  extends Direction("input") { override def flip: Direction = OUTPUT }
-object OUTPUT extends Direction("output") { override def flip: Direction = INPUT }
-object NO_DIR extends Direction("?") { override def flip: Direction = NO_DIR }
-
-@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
-object debug {  // scalastyle:ignore object.name
-  def apply (arg: Data): Data = arg
-}
-
-/** Mixing in this trait flips the direction of an Aggregate. */
-trait Flipped extends Data {
-  this.overrideDirection(_.flip, !_)
-}
-
-/** This forms the root of the type system for wire data types. The data value
-  * must be representable as some number (need not be known at Chisel compile
-  * time) of bits, and must have methods to pack / unpack structured data to /
-  * from bits.
-  */
-abstract class Data(dirArg: Direction) extends HasId {
-  def dir: Direction = dirVar
-
-  // Sucks this is mutable state, but cloneType doesn't take a Direction arg
-  private var isFlipVar = dirArg == INPUT
-  private var dirVar = dirArg
-  private[Chisel] def isFlip = isFlipVar
-
-  private[Chisel] def overrideDirection(newDir: Direction => Direction,
-                                        newFlip: Boolean => Boolean): this.type = {
-    this.isFlipVar = newFlip(this.isFlipVar)
-    for (field <- this.flatten)
-      (field: Data).dirVar = newDir((field: Data).dirVar)
-    this
-  }
-  def asInput: this.type = cloneType.overrideDirection(_ => INPUT, _ => true)
-  def asOutput: this.type = cloneType.overrideDirection(_ => OUTPUT, _ => false)
-  def flip(): this.type = cloneType.overrideDirection(_.flip, !_)
-
-  private[Chisel] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
-    throwException(s"cannot connect ${this} and ${that}")
-  private[Chisel] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
-    pushCommand(Connect(sourceInfo, this.lref, that.ref))
-  private[Chisel] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
-    pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
-  private[Chisel] def lref: Node = Node(this)
-  private[Chisel] def ref: Arg = if (isLit) litArg.get else lref
-  private[Chisel] def cloneTypeWidth(width: Width): this.type
-  private[Chisel] def toType: String
-
-  def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
-
-  def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
-
-  def cloneType: this.type
-  def litArg(): Option[LitArg] = None
-  def litValue(): BigInt = litArg.get.num
-  def isLit(): Boolean = litArg.isDefined
-
-  def width: Width
-  final def getWidth: Int = width.get
-
-  // While this being in the Data API doesn't really make sense (should be in
-  // Aggregate, right?) this is because of an implementation limitation:
-  // cloneWithDirection, which is private and defined here, needs flatten to
-  // set element directionality.
-  // Related: directionality is mutable state. A possible solution for both is
-  // to define directionality relative to the container, but these parent links
-  // currently don't exist (while this information may be available during
-  // FIRRTL emission, it would break directionality querying from Chisel, which
-  // does get used).
-  private[Chisel] def flatten: IndexedSeq[Bits]
-
-  /** Creates an new instance of this type, unpacking the input Bits into
-    * structured data.
-    *
-    * This performs the inverse operation of toBits.
-    *
-    * @note does NOT assign to the object this is called on, instead creates
-    * and returns a NEW object (useful in a clone-and-assign scenario)
-    * @note does NOT check bit widths, may drop bits during assignment
-    * @note what fromBits assigs to must have known widths
-    */
-  def fromBits(that: Bits): this.type = macro SourceInfoTransform.thatArg
-
-  def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = {
-    var i = 0
-    val wire = Wire(this.cloneType)
-    val bits =
-      if (that.width.known && that.width.get >= wire.width.get) {
-        that
-      } else {
-        Wire(that.cloneTypeWidth(wire.width), init = that)
-      }
-    for (x <- wire.flatten) {
-      x := bits(i + x.getWidth-1, i)
-      i += x.getWidth
-    }
-    wire.asInstanceOf[this.type]
-  }
-
-  /** Packs the value of this object as plain Bits.
-    *
-    * This performs the inverse operation of fromBits(Bits).
-    */
-  @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3")
-  def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo)
-
-  /** Reinterpret cast to a UInt.
-    *
-    * @note value not guaranteed to be preserved: for example, a SInt of width
-    * 3 and value -1 (0b111) would become an UInt with value 7
-    */
-  final def asUInt(): UInt = macro SourceInfoTransform.noArg
-
-  def do_asUInt(implicit sourceInfo: SourceInfo): UInt
-
-}
-
-object Wire {
-  def apply[T <: Data](t: T): T = macro WireTransform.apply[T]
-
-  // No source info since Scala macros don't yet support named / default arguments.
-  def apply[T <: Data](dummy: Int = 0, init: T): T =
-    do_apply(null.asInstanceOf[T], init)(UnlocatableSourceInfo)
-
-  // No source info since Scala macros don't yet support named / default arguments.
-  def apply[T <: Data](t: T, init: T): T =
-    do_apply(t, init)(UnlocatableSourceInfo)
-
-  def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = {
-    val x = Reg.makeType(t, null.asInstanceOf[T], init)
-    pushCommand(DefWire(sourceInfo, x))
-    pushCommand(DefInvalid(sourceInfo, x.ref))
-    if (init != null) {
-      x := init
-    }
-    x
-  }
-}
-
-object Clock {
-  def apply(dir: Direction = NO_DIR): Clock = new Clock(dir)
-}
-
-// TODO: Document this.
-sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
-  def cloneType: this.type = Clock(dirArg).asInstanceOf[this.type]
-  private[Chisel] override def flatten: IndexedSeq[Bits] = IndexedSeq()
-  private[Chisel] def cloneTypeWidth(width: Width): this.type = cloneType
-  private[Chisel] def toType = "Clock"
-
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: Clock => this connect that
-    case _ => this badConnect that
-  }
-
-  def do_asUInt(implicit sourceInfo: SourceInfo): UInt = {
-    throwException("clock cannot be interpreted as UInt")
-  }
-
-}
diff --git a/chiselFrontend/src/main/scala/Chisel/Module.scala b/chiselFrontend/src/main/scala/Chisel/Module.scala
deleted file mode 100644
index 20c9dd4a..00000000
--- a/chiselFrontend/src/main/scala/Chisel/Module.scala
+++ /dev/null
@@ -1,113 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-import scala.collection.mutable.{ArrayBuffer, HashSet}
-import scala.language.experimental.macros
-
-import internal._
-import internal.Builder.pushCommand
-import internal.Builder.dynamicContext
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
-
-object Module {
-  /** A wrapper method that all Module instantiations must be wrapped in
-    * (necessary to help Chisel track internal state).
-    *
-    * @param m the Module being created
-    *
-    * @return the input module `m` with Chisel metadata properly set
-    */
-  def apply[T <: Module](bc: => T): T = macro InstTransform.apply[T]
-
-  def do_apply[T <: Module](bc: => T)(implicit sourceInfo: SourceInfo): T = {
-    // Don't generate source info referencing parents inside a module, sincce this interferes with
-    // module de-duplication in FIRRTL emission.
-    val childSourceInfo = UnlocatableSourceInfo
-
-    val parent = dynamicContext.currentModule
-    val m = bc.setRefs()
-    m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs
-    dynamicContext.currentModule = parent
-    val ports = m.computePorts
-    Builder.components += Component(m, m.name, ports, m._commands)
-    pushCommand(DefInstance(sourceInfo, m, ports))
-    m.setupInParent(childSourceInfo)
-  }
-}
-
-/** Abstract base class for Modules, which behave much like Verilog modules.
-  * These may contain both logic and state which are written in the Module
-  * body (constructor).
-  *
-  * @note Module instantiations must be wrapped in a Module() call.
-  */
-abstract class Module(
-  override_clock: Option[Clock]=None, override_reset: Option[Bool]=None)
-extends HasId {
-  // _clock and _reset can be clock and reset in these 2ary constructors
-  // once chisel2 compatibility issues are resolved
-  def this(_clock: Clock) = this(Option(_clock), None)
-  def this(_reset: Bool)  = this(None, Option(_reset))
-  def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
-
-  private[Chisel] val _namespace = Builder.globalNamespace.child
-  private[Chisel] val _commands = ArrayBuffer[Command]()
-  private[Chisel] val _ids = ArrayBuffer[HasId]()
-  dynamicContext.currentModule = Some(this)
-
-  /** Name of the instance. */
-  val name = Builder.globalNamespace.name(getClass.getName.split('.').last)
-
-  /** IO for this Module. At the Scala level (pre-FIRRTL transformations),
-    * connections in and out of a Module may only go through `io` elements.
-    */
-  def io: Bundle
-  val clock = Clock(INPUT)
-  val reset = Bool(INPUT)
-
-  private[Chisel] def addId(d: HasId) { _ids += d }
-
-  private[Chisel] def ports: Seq[(String,Data)] = Vector(
-    ("clk", clock), ("reset", reset), ("io", io)
-  )
-
-  private[Chisel] def computePorts = for((name, port) <- ports) yield {
-    val bundleDir = if (port.isFlip) INPUT else OUTPUT
-    Port(port, if (port.dir == NO_DIR) bundleDir else port.dir)
-  }
-
-  private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
-    _parent match {
-      case Some(p) => {
-        pushCommand(DefInvalid(sourceInfo, io.ref)) // init instance inputs
-        clock := override_clock.getOrElse(p.clock)
-        reset := override_reset.getOrElse(p.reset)
-        this
-      }
-      case None => this
-    }
-  }
-
-  private[Chisel] def setRefs(): this.type = {
-    for ((name, port) <- ports) {
-      port.setRef(ModuleIO(this, _namespace.name(name)))
-    }
-
-    // Suggest names to nodes using runtime reflection
-    val valNames = HashSet[String](getClass.getDeclaredFields.map(_.getName):_*)
-    def isPublicVal(m: java.lang.reflect.Method) =
-      m.getParameterTypes.isEmpty && valNames.contains(m.getName)
-    val methods = getClass.getMethods.sortWith(_.getName > _.getName)
-    for (m <- methods; if isPublicVal(m)) m.invoke(this) match {
-      case (id: HasId) => id.suggestName(m.getName)
-      case _ =>
-    }
-
-    // All suggestions are in, force names to every node.
-    _ids.foreach(_.forceName(default="T", _namespace))
-    _ids.foreach(_._onModuleClose)
-    this
-  }
-}
diff --git a/chiselFrontend/src/main/scala/Chisel/Printf.scala b/chiselFrontend/src/main/scala/Chisel/Printf.scala
deleted file mode 100644
index f068f637..00000000
--- a/chiselFrontend/src/main/scala/Chisel/Printf.scala
+++ /dev/null
@@ -1,36 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-import scala.language.experimental.macros
-
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
-
-object printf { // scalastyle:ignore object.name
-  /** Prints a message in simulation.
-    *
-    * Does not fire when in reset (defined as the encapsulating Module's
-    * reset). If your definition of reset is not the encapsulating Module's
-    * reset, you will need to gate this externally.
-    *
-    * May be called outside of a Module (like defined in a function), so
-    * functions using printf make the standard Module assumptions (single clock
-    * and single reset).
-    *
-    * @param fmt printf format string
-    * @param data format string varargs containing data to print
-    */
-  def apply(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
-    when (!(Builder.dynamicContext.currentModule.get.reset)) {
-      printfWithoutReset(fmt, data:_*)
-    }
-  }
-
-  private[Chisel] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
-    val clock = Builder.dynamicContext.currentModule.get.clock
-    pushCommand(Printf(sourceInfo, Node(clock), fmt, data.map((d: Bits) => d.ref)))
-  }
-}
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala b/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala
deleted file mode 100644
index d0e28b7c..00000000
--- a/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala
+++ /dev/null
@@ -1,123 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel.internal
-
-import scala.util.DynamicVariable
-import scala.collection.mutable.{ArrayBuffer, HashMap}
-
-import Chisel._
-import Chisel.internal.firrtl._
-
-private[Chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
-  private var i = 0L
-  private val names = collection.mutable.HashSet[String]()
-
-  private def rename(n: String) = { i += 1; s"${n}_${i}" }
-
-  def contains(elem: String): Boolean = {
-    keywords.contains(elem) || names.contains(elem) ||
-      parent.map(_ contains elem).getOrElse(false)
-  }
-
-  def name(elem: String): String = {
-    if (this contains elem) {
-      name(rename(elem))
-    } else {
-      names += elem
-      elem
-    }
-  }
-
-  def child(kws: Set[String]): Namespace = new Namespace(Some(this), kws)
-  def child: Namespace = child(Set())
-}
-
-private[Chisel] class IdGen {
-  private var counter = -1L
-  def next: Long = {
-    counter += 1
-    counter
-  }
-}
-
-private[Chisel] trait HasId {
-  private[Chisel] def _onModuleClose {} // scalastyle:ignore method.name
-  private[Chisel] val _parent = Builder.dynamicContext.currentModule
-  _parent.foreach(_.addId(this))
-
-  private[Chisel] val _id = Builder.idGen.next
-  override def hashCode: Int = _id.toInt
-  override def equals(that: Any): Boolean = that match {
-    case x: HasId => _id == x._id
-    case _ => false
-  }
-
-  // Facilities for 'suggesting' a name to this.
-  // Post-name hooks called to carry the suggestion to other candidates as needed
-  private var suggested_name: Option[String] = None
-  private val postname_hooks = scala.collection.mutable.ListBuffer.empty[String=>Unit]
-  // Only takes the first suggestion!
-  def suggestName(name: =>String): this.type = {
-    if(suggested_name.isEmpty) suggested_name = Some(name)
-    for(hook <- postname_hooks) { hook(name) }
-    this
-  }
-  private[Chisel] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook
-
-  // Uses a namespace to convert suggestion into a true name
-  // Will not do any naming if the reference already assigned.
-  // (e.g. tried to suggest a name to part of a Bundle)
-  private[Chisel] def forceName(default: =>String, namespace: Namespace): Unit =
-    if(_ref.isEmpty) {
-      val candidate_name = suggested_name.getOrElse(default)
-      val available_name = namespace.name(candidate_name)
-      setRef(Ref(available_name))
-    }
-
-  private var _ref: Option[Arg] = None
-  private[Chisel] def setRef(imm: Arg): Unit = _ref = Some(imm)
-  private[Chisel] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
-  private[Chisel] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
-  private[Chisel] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
-  private[Chisel] def getRef: Arg = _ref.get
-}
-
-private[Chisel] class DynamicContext {
-  val idGen = new IdGen
-  val globalNamespace = new Namespace(None, Set())
-  val components = ArrayBuffer[Component]()
-  var currentModule: Option[Module] = None
-  val errors = new ErrorLog
-}
-
-private[Chisel] object Builder {
-  // All global mutable state must be referenced via dynamicContextVar!!
-  private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None)
-
-  def dynamicContext: DynamicContext =
-    dynamicContextVar.value getOrElse (new DynamicContext)
-  def idGen: IdGen = dynamicContext.idGen
-  def globalNamespace: Namespace = dynamicContext.globalNamespace
-  def components: ArrayBuffer[Component] = dynamicContext.components
-
-  def pushCommand[T <: Command](c: T): T = {
-    dynamicContext.currentModule.foreach(_._commands += c)
-    c
-  }
-  def pushOp[T <: Data](cmd: DefPrim[T]): T = pushCommand(cmd).id
-
-  def errors: ErrorLog = dynamicContext.errors
-  def error(m: => String): Unit = errors.error(m)
-
-  def build[T <: Module](f: => T): Circuit = {
-    dynamicContextVar.withValue(Some(new DynamicContext)) {
-      errors.info("Elaborating design...")
-      val mod = f
-      mod.forceName(mod.name, globalNamespace)
-      errors.checkpoint()
-      errors.info("Done elaborating.")
-
-      Circuit(components.last.name, components)
-    }
-  }
-}
diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index c0f8a354..5e88560c 100644
--- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -1,24 +1,26 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.collection.immutable.ListMap
 import scala.collection.mutable.{ArrayBuffer, HashSet, LinkedHashMap}
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform, UnlocatableSourceInfo}
 
 /** An abstract class for data types that solely consist of (are an aggregate
   * of) other Data objects.
   */
-sealed abstract class Aggregate(dirArg: Direction) extends Data(dirArg) {
-  private[Chisel] def cloneTypeWidth(width: Width): this.type = cloneType
-  def width: Width = flatten.map(_.width).reduce(_ + _)
+sealed abstract class Aggregate extends Data {
+  private[core] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[core] def width: Width = flatten.map(_.width).reduce(_ + _)
+  private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+    pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
 
-  def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten)
+  override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten)
 }
 
 object Vec {
@@ -26,10 +28,10 @@ object Vec {
     *
     * @note elements are NOT assigned by default and have no value
     */
-  def apply[T <: Data](n: Int, gen: T): Vec[T] = new Vec(gen.cloneType, n)
+  def apply[T <: Data](n: Int, gen: T): Vec[T] = new Vec(gen, n)
 
   @deprecated("Vec argument order should be size, t; this will be removed by the official release", "chisel3")
-  def apply[T <: Data](gen: T, n: Int): Vec[T] = new Vec(gen.cloneType, n)
+  def apply[T <: Data](gen: T, n: Int): Vec[T] = new Vec(gen, n)
 
   /** Creates a new [[Vec]] composed of elements of the input Seq of [[Data]]
     * nodes.
@@ -49,11 +51,30 @@ object Vec {
     // changing apply(elt0, elts*) to apply(elts*) causes a function collision
     // with apply(Seq) after type erasure. Workarounds by either introducing a
     // DummyImplicit or additional type parameter will break some code.
+
+    // Check that types are homogeneous.  Width mismatch for Elements is safe.
     require(!elts.isEmpty)
-    val width = elts.map(_.width).reduce(_ max _)
-    val vec = Wire(new Vec(elts.head.cloneTypeWidth(width), elts.length))
-    for ((v, e) <- vec zip elts)
-      v := e
+    def eltsCompatible(a: Data, b: Data) = a match {
+      case _: Element => a.getClass == b.getClass
+      case _: Aggregate => Mux.typesCompatible(a, b)
+    }
+
+    val t = elts.head
+    for (e <- elts.tail)
+      require(eltsCompatible(t, e), s"can't create Vec of heterogeneous types ${t.getClass} and ${e.getClass}")
+
+    val maxWidth = elts.map(_.width).reduce(_ max _)
+    val vec = Wire(new Vec(t.cloneTypeWidth(maxWidth), elts.length))
+    def doConnect(sink: T, source: T) = {
+      if (elts.head.flatten.exists(_.dir != Direction.Unspecified)) {
+        sink bulkConnect source
+      } else {
+        sink connect source
+      }
+    }
+    for ((v, e) <- vec zip elts) {
+      doConnect(v, e)
+    }
     vec
   }
 
@@ -91,10 +112,20 @@ object Vec {
     * @param gen function that generates the [[Data]] that becomes the output
     * element
     */
+  @deprecated("Vec.fill(n)(gen) is deprecated. Please use Vec(Seq.fill(n)(gen))", "chisel3")
   def fill[T <: Data](n: Int)(gen: => T): Vec[T] = macro VecTransform.fill
 
   def do_fill[T <: Data](n: Int)(gen: => T)(implicit sourceInfo: SourceInfo): Vec[T] =
     apply(Seq.fill(n)(gen))
+
+  /** Truncate an index to implement modulo-power-of-2 addressing. */
+  private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo): UInt = {
+    val w = BigInt(n-1).bitLength
+    if (n <= 1) UInt(0)
+    else if (idx.width.known && idx.width.get <= w) idx
+    else if (idx.width.known) idx(w-1,0)
+    else Wire(UInt(width = w), init = idx)
+  }
 }
 
 /** A vector (array) of [[Data]] elements. Provides hardware versions of various
@@ -106,49 +137,70 @@ object Vec {
   * @note Vecs, unlike classes in Scala's collection library, are propagated
   * intact to FIRRTL as a vector type, which may make debugging easier
   */
-sealed class Vec[T <: Data] private (gen: => T, val length: Int)
-    extends Aggregate(gen.dir) with VecLike[T] {
+sealed class Vec[T <: Data] private (gen: T, val length: Int)
+    extends Aggregate with VecLike[T] {
   // Note: the constructor takes a gen() function instead of a Seq to enforce
   // that all elements must be the same and because it makes FIRRTL generation
   // simpler.
+  private val self: Seq[T] = Vector.fill(length)(gen.chiselCloneType)
 
-  private val self = IndexedSeq.fill(length)(gen)
+  /**
+  * sample_element 'tracks' all changes to the elements of self.
+  * For consistency, sample_element is always used for creating dynamically
+  * indexed ports and outputing the FIRRTL type.
+  *
+  * Needed specifically for the case when the Vec is length 0.
+  */
+  private[core] val sample_element: T = gen.chiselCloneType
 
-  override def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this := that
+  // allElements current includes sample_element
+  // This is somewhat weird although I think the best course of action here is
+  // to deprecate allElements in favor of dispatched functions to Data or
+  // a pattern matched recursive descent
+  private[chisel3] final def allElements: Seq[Element] =
+    (sample_element +: self).flatMap(_.allElements)
 
   /** Strong bulk connect, assigning elements in this Vec from elements in a Seq.
     *
     * @note the length of this Vec must match the length of the input Seq
     */
-  def <> (that: Seq[T])(implicit sourceInfo: SourceInfo): Unit = this := that
+  def <> (that: Seq[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = {
+    require(this.length == that.length)
+    for ((a, b) <- this zip that)
+      a <> b
+  }
 
   // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data
-  def <> (that: Vec[T])(implicit sourceInfo: SourceInfo): Unit = this := that.asInstanceOf[Data]
-
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: Vec[_] => this connect that
-    case _ => this badConnect that
-  }
+  def <> (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = this bulkConnect that.asInstanceOf[Data]
 
   /** Strong bulk connect, assigning elements in this Vec from elements in a Seq.
     *
     * @note the length of this Vec must match the length of the input Seq
     */
-  def := (that: Seq[T])(implicit sourceInfo: SourceInfo): Unit = {
+  def := (that: Seq[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = {
     require(this.length == that.length)
     for ((a, b) <- this zip that)
       a := b
   }
 
   // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data
-  def := (that: Vec[T])(implicit sourceInfo: SourceInfo): Unit = this connect that
+  def := (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = this connect that
 
   /** Creates a dynamically indexed read or write accessor into the array.
     */
   def apply(idx: UInt): T = {
-    val x = gen
-    x.setRef(this, idx)
-    x
+    Binding.checkSynthesizable(idx ,s"'idx' ($idx)")
+    val port = sample_element.chiselCloneType
+    val i = Vec.truncateIndex(idx, length)(UnlocatableSourceInfo)
+    port.setRef(this, i)
+
+    // Bind each element of port to being whatever the base type is
+    // Using the head element as the sample_element
+    for((port_elem, model_elem) <- port.allElements zip sample_element.allElements) {
+      port_elem.binding = model_elem.binding
+    }
+
+    port
   }
 
   /** Creates a statically indexed read or write accessor into the array.
@@ -159,18 +211,31 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
   def read(idx: UInt): T = apply(idx)
 
   @deprecated("Use Vec.apply instead", "chisel3")
-  def write(idx: UInt, data: T): Unit = apply(idx).:=(data)(DeprecatedSourceInfo)
+  def write(idx: UInt, data: T): Unit = {
+    apply(idx).:=(data)(DeprecatedSourceInfo, chisel3.core.ExplicitCompileOptions.NotStrict)
+  }
 
-  override def cloneType: this.type =
+  override def cloneType: this.type = {
     Vec(length, gen).asInstanceOf[this.type]
+  }
 
-  private val t = gen
-  private[Chisel] def toType: String = s"${t.toType}[$length]"
-  private[Chisel] lazy val flatten: IndexedSeq[Bits] =
+  private[chisel3] def toType: String = s"${sample_element.toType}[$length]"
+  private[chisel3] lazy val flatten: IndexedSeq[Bits] =
     (0 until length).flatMap(i => this.apply(i).flatten)
 
   for ((elt, i) <- self zipWithIndex)
     elt.setRef(this, i)
+
+  /** Default "pretty-print" implementation
+    * Analogous to printing a Seq
+    * Results in "Vec(elt0, elt1, ...)"
+    */
+  def toPrintable: Printable = {
+    val elts =
+      if (length == 0) List.empty[Printable]
+      else self flatMap (e => List(e.toPrintable, PString(", "))) dropRight 1
+    PString("Vec(") + Printables(elts) + PString(")")
+  }
 }
 
 /** A trait for [[Vec]]s containing common hardware generators for collection
@@ -258,7 +323,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
   * Usage: extend this class (either as an anonymous or named class) and define
   * members variables of [[Data]] subtypes to be elements in the Bundle.
   */
-class Bundle extends Aggregate(NO_DIR) {
+class Bundle extends Aggregate {
   private val _namespace = Builder.globalNamespace.child
 
   // TODO: replace with better defined FIRRTL weak-connect operator
@@ -274,13 +339,6 @@ class Bundle extends Aggregate(NO_DIR) {
     * mySubModule.io <> io
     * }}}
     */
-  override def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: Bundle => this bulkConnect that
-    case _ => this badConnect that
-  }
-
-  // TODO: replace with better defined FIRRTL strong-connect operator
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this <> that
 
   lazy val elements: ListMap[String, Data] = ListMap(namedElts:_*)
 
@@ -317,7 +375,7 @@ class Bundle extends Aggregate(NO_DIR) {
 
   /** Returns a list of elements in this Bundle.
     */
-  private[Chisel] lazy val namedElts = {
+  private[core] lazy val namedElts = {
     val nameMap = LinkedHashMap[String, Data]()
     val seen = HashSet[Data]()
     for (m <- getClass.getMethods.sortWith(_.getName < _.getName)) {
@@ -333,19 +391,20 @@ class Bundle extends Aggregate(NO_DIR) {
     }
     ArrayBuffer(nameMap.toSeq:_*) sortWith {case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn))}
   }
-  private[Chisel] def toType = {
+  private[chisel3] def toType = {
     def eltPort(elt: Data): String = {
-      val flipStr = if (elt.isFlip) "flip " else ""
+      val flipStr: String = if(Data.isFirrtlFlipped(elt)) "flip " else ""
       s"${flipStr}${elt.getRef.name} : ${elt.toType}"
     }
     s"{${namedElts.reverse.map(e => eltPort(e._2)).mkString(", ")}}"
   }
-  private[Chisel] lazy val flatten = namedElts.flatMap(_._2.flatten)
-  private[Chisel] def addElt(name: String, elt: Data): Unit =
+  private[chisel3] lazy val flatten = namedElts.flatMap(_._2.flatten)
+  private[core] def addElt(name: String, elt: Data): Unit =
     namedElts += name -> elt
-
-  private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name
+  private[chisel3] override def _onModuleClose: Unit = // scalastyle:ignore method.name
     for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) }
+    
+  private[chisel3] final def allElements: Seq[Element] = namedElts.flatMap(_._2.allElements)
 
   override def cloneType : this.type = {
     // If the user did not provide a cloneType method, try invoking one of
@@ -373,8 +432,24 @@ class Bundle extends Aggregate(NO_DIR) {
         this
     }
   }
+
+  /** Default "pretty-print" implementation
+    * Analogous to printing a Map
+    * Results in "Bundle(elt0.name -> elt0.value, ...)"
+    */
+  def toPrintable: Printable = {
+    val elts =
+      if (elements.isEmpty) List.empty[Printable]
+      else {
+        elements.toList.reverse flatMap { case (name, data) =>
+          List(PString(s"$name -> "), data.toPrintable, PString(", "))
+        } dropRight 1 // Remove trailing ", "
+      }
+    PString("Bundle(") + Printables(elts) + PString(")")
+  }
 }
 
-private[Chisel] object Bundle {
-  val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits")
+private[core] object Bundle {
+  val keywords = List("flip", "asInput", "asOutput", "cloneType", "chiselCloneType", "toBits",
+    "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent")
 }
diff --git a/chiselFrontend/src/main/scala/Chisel/Assert.scala b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
index c086f014..4782a845 100644
--- a/chiselFrontend/src/main/scala/Chisel/Assert.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
@@ -1,14 +1,14 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.reflect.macros.blackbox.Context
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.SourceInfo
 
 object assert { // scalastyle:ignore object.name
   /** Checks for a condition to be valid in the circuit at all times. If the
@@ -24,21 +24,22 @@ object assert { // scalastyle:ignore object.name
     *
     * @param cond condition, assertion fires (simulation fails) when false
     * @param message optional message to print when the assertion fires
+    * @param data optional bits to print in the message formatting
     *
     * @note currently cannot be used in core Chisel / libraries because macro
     * defs need to be compiled first and the SBT project is not set up to do
     * that
     */
   // Macros currently can't take default arguments, so we need two functions to emulate defaults.
-  def apply(cond: Bool, message: String)(implicit sourceInfo: SourceInfo): Unit = macro apply_impl_msg
+  def apply(cond: Bool, message: String, data: Bits*)(implicit sourceInfo: SourceInfo): Unit = macro apply_impl_msg_data
   def apply(cond: Bool)(implicit sourceInfo: SourceInfo): Unit = macro apply_impl
 
-  def apply_impl_msg(c: Context)(cond: c.Tree, message: c.Tree)(sourceInfo: c.Tree): c.Tree = {
+  def apply_impl_msg_data(c: Context)(cond: c.Tree, message: c.Tree, data: c.Tree*)(sourceInfo: c.Tree): c.Tree = {
     import c.universe._
     val p = c.enclosingPosition
     val condStr = s"${p.source.file.name}:${p.line} ${p.lineContent.trim}"
     val apply_impl_do = symbolOf[this.type].asClass.module.info.member(TermName("apply_impl_do"))
-    q"$apply_impl_do($cond, $condStr, _root_.scala.Some($message))($sourceInfo)"
+    q"$apply_impl_do($cond, $condStr, _root_.scala.Some($message), ..$data)($sourceInfo)"
   }
 
   def apply_impl(c: Context)(cond: c.Tree)(sourceInfo: c.Tree): c.Tree = {
@@ -49,13 +50,13 @@ object assert { // scalastyle:ignore object.name
     q"$apply_impl_do($cond, $condStr, _root_.scala.None)($sourceInfo)"
   }
 
-  def apply_impl_do(cond: Bool, line: String, message: Option[String])(implicit sourceInfo: SourceInfo) {
-    when (!(cond || Builder.dynamicContext.currentModule.get.reset)) {
+  def apply_impl_do(cond: Bool, line: String, message: Option[String], data: Bits*)(implicit sourceInfo: SourceInfo) {
+    when (!(cond || Builder.forcedModule.reset)) {
       message match {
-        case Some(str) => printf.printfWithoutReset(s"Assertion failed: $str\n    at $line\n")
-        case None => printf.printfWithoutReset(s"Assertion failed\n    at $line\n")
+        case Some(str) => printf.printfWithoutReset(s"Assertion failed: $str\n    at $line\n", data:_*)
+        case None => printf.printfWithoutReset(s"Assertion failed\n    at $line\n", data:_*)
       }
-      pushCommand(Stop(sourceInfo, Node(Builder.dynamicContext.currentModule.get.clock), 1))
+      pushCommand(Stop(sourceInfo, Node(Builder.forcedModule.clock), 1))
     }
   }
 
@@ -71,3 +72,17 @@ object assert { // scalastyle:ignore object.name
     Predef.assert(cond, "")
   }
 }
+
+object stop { // scalastyle:ignore object.name
+  /** Terminate execution with a failure code. */
+  def apply(code: Int)(implicit sourceInfo: SourceInfo): Unit = {
+    when (!Builder.forcedModule.reset) {
+      pushCommand(Stop(sourceInfo, Node(Builder.forcedModule.clock), code))
+    }
+  }
+
+  /** Terminate execution, indicating success. */
+  def apply()(implicit sourceInfo: SourceInfo): Unit = {
+    stop(0)
+  }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
new file mode 100644
index 00000000..2599a20a
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -0,0 +1,238 @@
+// See LICENSE for license details.
+
+package chisel3.core
+
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl.Connect
+import scala.language.experimental.macros
+import chisel3.internal.sourceinfo._
+
+/**
+* BiConnect.connect executes a bidirectional connection element-wise.
+*
+* Note that the arguments are left and right (not source and sink) so the
+* intent is for the operation to be commutative.
+*
+* The connect operation will recurse down the left Data (with the right Data).
+* An exception will be thrown if a movement through the left cannot be matched
+* in the right (or if the right side has extra fields).
+*
+* See elemConnect for details on how the root connections are issued.
+*
+*/
+
+object BiConnect {
+  // These are all the possible exceptions that can be thrown.
+  case class BiConnectException(message: String) extends Exception(message)
+  // These are from element-level connection
+  def BothDriversException =
+    BiConnectException(": Both Left and Right are drivers")
+  def NeitherDriverException =
+    BiConnectException(": Neither Left nor Right is a driver")
+  def UnknownDriverException =
+    BiConnectException(": Locally unclear whether Left or Right (both internal)")
+  def UnknownRelationException =
+    BiConnectException(": Left or Right unavailable to current module.")
+  // These are when recursing down aggregate types
+  def MismatchedVecException =
+    BiConnectException(": Left and Right are different length Vecs.")
+  def MissingLeftFieldException(field: String) =
+    BiConnectException(s".$field: Left Bundle missing field ($field).")
+  def MissingRightFieldException(field: String) =
+    BiConnectException(s": Right Bundle missing field ($field).")
+  def MismatchedException(left: String, right: String) =
+    BiConnectException(s": Left ($left) and Right ($right) have different types.")
+
+  /** This function is what recursively tries to connect a left and right together
+  *
+  * There is some cleverness in the use of internal try-catch to catch exceptions
+  * during the recursive decent and then rethrow them with extra information added.
+  * This gives the user a 'path' to where in the connections things went wrong.
+  */
+  def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: Module): Unit =
+    (left, right) match {
+      // Handle element case (root case)
+      case (left_e: Element, right_e: Element) => {
+        elemConnect(sourceInfo, connectCompileOptions, left_e, right_e, context_mod)
+        // TODO(twigg): Verify the element-level classes are connectable
+      }
+      // Handle Vec case
+      case (left_v: Vec[Data @unchecked], right_v: Vec[Data @unchecked]) => {
+        if(left_v.length != right_v.length) { throw MismatchedVecException }
+        for(idx <- 0 until left_v.length) {
+          try {
+            connect(sourceInfo, connectCompileOptions, left_v(idx), right_v(idx), context_mod)
+          } catch {
+            case BiConnectException(message) => throw BiConnectException(s"($idx)$message")
+          }
+        }
+      }
+      // Handle Bundle case
+      case (left_b: Bundle, right_b: Bundle) => {
+        // Verify right has no extra fields that left doesn't have
+        for((field, right_sub) <- right_b.elements) {
+          if(!left_b.elements.isDefinedAt(field)) {
+            if (connectCompileOptions.connectFieldsMustMatch) {
+              throw MissingLeftFieldException(field)
+            }
+          }
+        }
+        // For each field in left, descend with right
+        for((field, left_sub) <- left_b.elements) {
+          try {
+            right_b.elements.get(field) match {
+              case Some(right_sub) => connect(sourceInfo, connectCompileOptions, left_sub, right_sub, context_mod)
+              case None => {
+                if (connectCompileOptions.connectFieldsMustMatch) {
+                  throw MissingRightFieldException(field)
+                }
+              }
+            }
+          } catch {
+            case BiConnectException(message) => throw BiConnectException(s".$field$message")
+          }
+        }
+      }
+      // Left and right are different subtypes of Data so fail
+      case (left, right) => throw MismatchedException(left.toString, right.toString)
+    }
+
+  // These functions (finally) issue the connection operation
+  // Issue with right as sink, left as source
+  private def issueConnectL2R(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = {
+    pushCommand(Connect(sourceInfo, right.lref, left.ref))
+  }
+  // Issue with left as sink, right as source
+  private def issueConnectR2L(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = {
+    pushCommand(Connect(sourceInfo, left.lref, right.ref))
+  }
+
+  // This function checks if element-level connection operation allowed.
+  // Then it either issues it or throws the appropriate exception.
+  def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: Module): Unit = {
+    import Direction.{Input, Output} // Using extensively so import these
+    // If left or right have no location, assume in context module
+    // This can occur if one of them is a literal, unbound will error previously
+    val left_mod: Module  = left.binding.location.getOrElse(context_mod)
+    val right_mod: Module = right.binding.location.getOrElse(context_mod)
+
+    val left_direction: Option[Direction] = left.binding.direction
+    val right_direction: Option[Direction] = right.binding.direction
+    // None means internal
+
+    // CASE: Context is same module as left node and right node is in a child module
+    if( (left_mod == context_mod) &&
+        (right_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, right node better be a port node and thus have a direction hint
+      ((left_direction, right_direction): @unchecked) match {
+        //    CURRENT MOD   CHILD MOD
+        case (Some(Input),  Some(Input))  => issueConnectL2R(left, right)
+        case (None,         Some(Input))  => issueConnectL2R(left, right)
+
+        case (Some(Output), Some(Output)) => issueConnectR2L(left, right)
+        case (None,         Some(Output)) => issueConnectR2L(left, right)
+
+        case (Some(Input),  Some(Output)) => throw BothDriversException
+        case (Some(Output), Some(Input))  => throw NeitherDriverException
+        case (_,            None)         => throw UnknownRelationException
+      }
+    }
+
+    // CASE: Context is same module as right node and left node is in child module
+    else if( (right_mod == context_mod) &&
+             (left_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, left node better be a port node and thus have a direction hint
+      ((left_direction, right_direction): @unchecked) match {
+        //    CHILD MOD     CURRENT MOD
+        case (Some(Input),  Some(Input))  => issueConnectR2L(left, right)
+        case (Some(Input),  None)         => issueConnectR2L(left, right)
+
+        case (Some(Output), Some(Output)) => issueConnectL2R(left, right)
+        case (Some(Output), None)         => issueConnectL2R(left, right)
+
+        case (Some(Input),  Some(Output)) => throw NeitherDriverException
+        case (Some(Output), Some(Input))  => throw BothDriversException
+        case (None, _)                    => throw UnknownRelationException
+      }
+    }
+
+    // CASE: Context is same module that both left node and right node are in
+    else if( (context_mod == left_mod) && (context_mod == right_mod) ) {
+      ((left_direction, right_direction): @unchecked) match {
+        //    CURRENT MOD   CURRENT MOD
+        case (Some(Input),  Some(Output)) => issueConnectL2R(left, right)
+        case (Some(Input),  None)         => issueConnectL2R(left, right)
+        case (None,         Some(Output)) => issueConnectL2R(left, right)
+
+        case (Some(Output), Some(Input))  => issueConnectR2L(left, right)
+        case (Some(Output), None)         => issueConnectR2L(left, right)
+        case (None,         Some(Input))  => issueConnectR2L(left, right)
+
+        case (Some(Input),  Some(Input))  => {
+          if (connectCompileOptions.dontAssumeDirectionality) {
+            throw BothDriversException
+          } else {
+            (left.binding, right.binding) match {
+              case (PortBinding(_, _), PortBinding(_, _)) => throw BothDriversException
+              case (PortBinding(_, _), _) => issueConnectL2R(left, right)
+              case (_, PortBinding(_, _)) => issueConnectR2L(left, right)
+              case _ => throw BothDriversException
+            }
+          }
+        }
+        case (Some(Output), Some(Output)) => {
+          if (connectCompileOptions.dontAssumeDirectionality) {
+            throw BothDriversException
+          } else {
+            (left.binding, right.binding) match {
+              case (PortBinding(_, _), PortBinding(_, _)) => throw BothDriversException
+              case (PortBinding(_, _), _) => issueConnectR2L(left, right)
+              case (_, PortBinding(_, _)) => issueConnectL2R(left, right)
+              case _ => throw BothDriversException
+            }
+          }
+        }
+        case (None,         None)         => {
+          if (connectCompileOptions.dontAssumeDirectionality) {
+            throw UnknownDriverException
+          } else {
+            issueConnectR2L(left, right)
+          }
+        }
+      }
+    }
+
+    // CASE: Context is the parent module of both the module containing left node
+    //                                        and the module containing right node
+    //   Note: This includes case when left and right in same module but in parent
+    else if( (left_mod._parent.map(_ == context_mod).getOrElse(false)) &&
+             (right_mod._parent.map(_ == context_mod).getOrElse(false))
+    ) {
+      // Thus both nodes must be ports and have a direction hint
+      ((left_direction, right_direction): @unchecked) match {
+        //    CHILD MOD     CHILD MOD
+        case (Some(Input),  Some(Output)) => issueConnectR2L(left, right)
+        case (Some(Output), Some(Input))  => issueConnectL2R(left, right)
+
+        case (Some(Input),  Some(Input))  => throw NeitherDriverException
+        case (Some(Output), Some(Output)) => throw BothDriversException
+        case (_, None)                    =>
+          if (connectCompileOptions.dontAssumeDirectionality) {
+            throw UnknownRelationException
+          } else {
+            issueConnectR2L(left, right)
+          }
+        case (None, _)                    =>
+          if (connectCompileOptions.dontAssumeDirectionality) {
+            throw UnknownRelationException
+          } else {
+            issueConnectR2L(left, right)
+          }
+      }
+    }
+
+    // Not quite sure where left and right are compared to current module
+    // so just error out
+    else throw UnknownRelationException
+  }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala
new file mode 100644
index 00000000..c7346dce
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala
@@ -0,0 +1,64 @@
+package chisel3.core
+
+/**
+* A Binder is a function from UnboundBinding to some Binding.
+*
+* These are used exclusively by Binding.bind and sealed in order to keep
+* all of them in one place. There are two flavors of Binders:
+* Non-terminal (returns another UnboundBinding): These are used to reformat an
+*   UnboundBinding (like setting direction) before it is terminally bound.
+* Terminal (returns any other Binding): Due to the nature of Bindings, once a
+*   Data is bound to anything but an UnboundBinding, it is forever locked to
+*   being that type (as it now represents something in the hardware graph).
+*
+* Note that some Binders require extra arguments to be constructed, like the
+* enclosing Module.
+*/
+
+sealed trait Binder[Out <: Binding] extends Function1[UnboundBinding, Out]{
+  def apply(in: UnboundBinding): Out
+}
+
+// THE NON-TERMINAL BINDERS
+// These 'rebind' to another unbound node of different direction!
+case object InputBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(Some(Direction.Input))
+}
+case object OutputBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(Some(Direction.Output))
+}
+case object FlippedBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(in.direction.map(_.flip))
+  // TODO(twigg): flipping a None should probably be a warning/error
+}
+// The need for this should be transient.
+case object NoDirectionBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(None)
+}
+
+// THE TERMINAL BINDERS
+case object LitBinder extends Binder[LitBinding] {
+  def apply(in: UnboundBinding) = LitBinding()
+}
+
+case class MemoryPortBinder(enclosure: Module) extends Binder[MemoryPortBinding] {
+  def apply(in: UnboundBinding) = MemoryPortBinding(enclosure)
+}
+
+case class OpBinder(enclosure: Module) extends Binder[OpBinding] {
+  def apply(in: UnboundBinding) = OpBinding(enclosure)
+}
+
+// Notice how PortBinder uses the direction of the UnboundNode
+case class PortBinder(enclosure: Module) extends Binder[PortBinding] {
+  def apply(in: UnboundBinding) = PortBinding(enclosure, in.direction)
+}
+
+case class RegBinder(enclosure: Module) extends Binder[RegBinding] {
+  def apply(in: UnboundBinding) = RegBinding(enclosure)
+}
+
+case class WireBinder(enclosure: Module) extends Binder[WireBinding] {
+  def apply(in: UnboundBinding) = WireBinding(enclosure)
+}
+
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
new file mode 100644
index 00000000..5378f3ae
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -0,0 +1,211 @@
+package chisel3.core
+
+import chisel3.internal.Builder.{forcedModule}
+
+/**
+ * The purpose of a Binding is to indicate what type of hardware 'entity' a
+ * specific Data's leaf Elements is actually bound to. All Data starts as being
+ * Unbound (and the whole point of cloneType is to return an unbound version).
+ * Then, specific API calls take a Data, and return a bound version (either by
+ * binding the original model or cloneType then binding the clone). For example,
+ * Reg[T<:Data](...) returns a T bound to RegBinding.
+ *
+ * It is considered invariant that all Elements of a single Data are bound to
+ * the same concrete type of Binding.
+ *
+ * These bindings can be checked (e.g. checkSynthesizable) to make sure certain
+ * operations are valid. For example, arithemetic operations or connections can
+ * only be executed between synthesizable nodes. These checks are to avoid
+ * undefined reference errors.
+ *
+ * Bindings can carry information about the particular element in the graph it
+ * represents like:
+ * - For ports (and unbound), the 'direction'
+ * - For (relevant) synthesizable nodes, the enclosing Module
+ *
+ * TODO(twigg): Enrich the bindings to carry more information like the hosting
+ * module (when applicable), direction (when applicable), literal info (when
+ * applicable). Can ensure applicable data only stored on relevant nodes. e.g.
+ * literal info on LitBinding, direction info on UnboundBinding and PortBinding,
+ * etc.
+ *
+ * TODO(twigg): Currently, bindings only apply at the Element level and an
+ * Aggregate is considered bound via its elements. May be appropriate to allow
+ * Aggregates to be bound along with the Elements. However, certain literal and
+ * port direction information doesn't quite make sense in aggregates. This would
+ * elegantly handle the empty Vec or Bundle problem though.
+ *
+ * TODO(twigg): Binding is currently done via allElements. It may be more
+ * elegant if this was instead done as a more explicit tree walk as that allows
+ * for better errors.
+ */
+
+object Binding {
+  // Two bindings are 'compatible' if they are the same type.
+  // Check currently kind of weird: just ensures same class
+  private def compatible(a: Binding, b: Binding): Boolean = a.getClass == b.getClass
+  private def compatible(nodes: Seq[Binding]): Boolean =
+    if(nodes.size > 1)
+      (for((a,b) <- nodes zip nodes.tail) yield compatible(a,b))
+      .fold(true)(_&&_)
+    else true
+
+  case class BindingException(message: String) extends Exception(message)
+  def AlreadyBoundException(binding: String) = BindingException(s": Already bound to $binding")
+  def NotSynthesizableException = BindingException(s": Not bound to synthesizable node, currently only Type description")
+
+  // This recursively walks down the Data tree to look at all the leaf 'Element's
+  // Will build up an error string in case something goes wrong
+  // TODO(twigg): Make member function of Data.
+  //   Allows oddities like sample_element to be better hidden
+  private def walkToBinding(target: Data, checker: Element=>Unit): Unit = target match {
+    case (element: Element) => checker(element)
+    case (vec: Vec[Data @unchecked]) => {
+      try walkToBinding(vec.sample_element, checker)
+      catch {
+        case BindingException(message) => throw BindingException(s"(*)$message")
+      }
+      for(idx <- 0 until vec.length) {
+        try walkToBinding(vec(idx), checker)
+        catch {
+          case BindingException(message) => throw BindingException(s"($idx)$message")
+        }
+      }
+    }
+    case (bundle: Bundle) => {
+      for((field, subelem) <- bundle.elements) {
+        try walkToBinding(subelem, checker)
+        catch {
+          case BindingException(message) => throw BindingException(s".$field$message")
+        }
+      }
+    }
+  }
+
+  // Use walkToBinding to actually rebind the node type
+  def bind[T<:Data](target: T, binder: Binder[_<:Binding], error_prelude: String): target.type = {
+    try walkToBinding(
+      target,
+      element => element.binding match {
+        case unbound @ UnboundBinding(_) => {
+          element.binding = binder(unbound)
+        }
+          // If autoIOWrap is enabled and we're rebinding a PortBinding, just ignore the rebinding.
+        case portBound @ PortBinding(_, _) if (!(forcedModule.compileOptions.requireIOWrap) && binder.isInstanceOf[PortBinder]) =>
+        case binding => throw AlreadyBoundException(binding.toString)
+      }
+    )
+    catch {
+      case BindingException(message) => throw BindingException(s"$error_prelude$message")
+    }
+    target
+  }
+
+  // Excepts if any root element is already bound
+  def checkUnbound(target: Data, error_prelude: String): Unit = {
+    try walkToBinding(
+      target,
+      element => element.binding match {
+        case unbound @ UnboundBinding(_) => {}
+        case binding => throw AlreadyBoundException(binding.toString)
+      }
+    )
+    catch {
+      case BindingException(message) => throw BindingException(s"$error_prelude$message")
+    }
+  }
+
+  // Excepts if any root element is unbound and thus not on the hardware graph
+  def checkSynthesizable(target: Data, error_prelude: String): Unit = {
+    // This is called if we support autoIOWrap
+    def elementOfIO(element: Element): Boolean = {
+      element._parent match {
+        case None => false
+        case Some(x: Module) => {
+          // Have we defined the IO ports for this module? If not, do so now.
+          if (!x.ioDefined) {
+            x.computePorts
+            element.binding match {
+              case SynthesizableBinding() => true
+              case _ => false
+            }
+          } else {
+            // io.flatten eliminates Clock elements, so we need to use io.allElements
+            val ports = x.io.allElements
+            val isIOElement = ports.contains(element) || element == x.clock || element == x.reset
+            isIOElement
+          }
+        }
+      }
+    }
+    try walkToBinding(
+      target,
+      element => element.binding match {
+        case SynthesizableBinding() => {} // OK
+        case binding =>
+          // The following kludge is an attempt to provide backward compatibility
+          // It should be done at at higher level.
+          if ((forcedModule.compileOptions.requireIOWrap || !elementOfIO(element)))
+            throw NotSynthesizableException
+          else
+            Binding.bind(element, PortBinder(element._parent.get), "Error: IO")
+      }
+    )
+    catch {
+      case BindingException(message) => throw BindingException(s"$error_prelude$message")
+    }
+  }
+}
+
+// Location refers to 'where' in the Module hierarchy this lives
+sealed trait Binding {
+  def location: Option[Module]
+  def direction: Option[Direction]
+}
+
+// Constrained-ness refers to whether 'bound by Module boundaries'
+// An unconstrained binding, like a literal, can be read by everyone
+sealed trait UnconstrainedBinding extends Binding {
+  def location = None
+}
+// A constrained binding can only be read/written by specific modules
+// Location will track where this Module is
+sealed trait ConstrainedBinding extends Binding {
+  def enclosure: Module
+  def location = Some(enclosure)
+}
+
+// An undirectioned binding means the element represents an internal node
+//   with no meaningful concept of a direction
+sealed trait UndirectionedBinding extends Binding { def direction = None }
+
+// This is the default binding, represents data not yet positioned in the graph
+case class UnboundBinding(direction: Option[Direction])
+    extends Binding with UnconstrainedBinding
+
+
+// A synthesizable binding is 'bound into' the hardware graph
+object SynthesizableBinding {
+  def unapply(target: Binding): Boolean = target.isInstanceOf[SynthesizableBinding]
+  // Type check OK because Binding and SynthesizableBinding is sealed
+}
+sealed trait SynthesizableBinding extends Binding
+case class LitBinding() // will eventually have literal info
+    extends SynthesizableBinding with UnconstrainedBinding with UndirectionedBinding
+
+case class MemoryPortBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
+
+// TODO(twigg): Ops between unenclosed nodes can also be unenclosed
+// However, Chisel currently binds all op results to a module
+case class OpBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
+
+case class PortBinding(enclosure: Module, direction: Option[Direction])
+    extends SynthesizableBinding with ConstrainedBinding
+
+case class RegBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
+
+case class WireBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
diff --git a/chiselFrontend/src/main/scala/Chisel/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index ee6b1dee..00d0cc14 100644
--- a/chiselFrontend/src/main/scala/Chisel/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -1,38 +1,65 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushOp
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform,
+import chisel3.internal._
+import chisel3.internal.Builder.{pushCommand, pushOp}
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform,
   UIntTransform, MuxTransform}
-import firrtl.PrimOp._
+import chisel3.internal.firrtl.PrimOp._
+// TODO: remove this once we have CompileOptions threaded through the macro system.
+import chisel3.core.ExplicitCompileOptions.NotStrict
 
 /** Element is a leaf data type: it cannot contain other Data objects. Example
   * uses are for representing primitive data types, like integers and bits.
   */
-abstract class Element(dirArg: Direction, val width: Width) extends Data(dirArg)
+abstract class Element(private[core] val width: Width) extends Data {
+  /**
+   * Elements can actually be bound to the hardware graph and thus must store
+   * that binding information.
+   */
+  private[this] var _binding: Binding = UnboundBinding(None)
+  // Define setter/getter pairing
+  // Can only bind something that has not yet been bound.
+  private[core] def binding_=(target: Binding): Unit = _binding match {
+    case UnboundBinding(_) => {
+      _binding = target
+      _binding
+    }
+    case _ => throw Binding.AlreadyBoundException(_binding.toString)
+      // Other checks should have caught this.
+  }
+  private[core] def binding = _binding
+
+  /** Return the binding for some bits. */
+  def dir: Direction = binding.direction.getOrElse(Direction.Unspecified)
+
+  private[chisel3] final def allElements: Seq[Element] = Seq(this)
+  def widthKnown: Boolean = width.known
+  def name: String = getRef.name
+
+  private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+    pushCommand(Connect(sourceInfo, this.lref, that.ref))
+}
 
 /** A data type for values represented by a single bitvector. Provides basic
   * bitwise operations.
   */
-sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: Option[LitArg])
-    extends Element(dirArg, width) {
+sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
+    extends Element(width) {
   // TODO: perhaps make this concrete?
   // Arguments for: self-checking code (can't do arithmetic on bits)
   // Arguments against: generates down to a FIRRTL UInt anyways
 
-  private[Chisel] def fromInt(x: BigInt, w: Int): this.type
+  private[chisel3] def fromInt(x: BigInt, w: Int): this.type
 
-  private[Chisel] def flatten: IndexedSeq[Bits] = IndexedSeq(this)
+  private[chisel3] def flatten: IndexedSeq[Bits] = IndexedSeq(this)
 
   def cloneType: this.type = cloneTypeWidth(width)
 
-  override def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this := that
-
   final def tail(n: Int): UInt = macro SourceInfoTransform.nArg
   final def head(n: Int): UInt = macro SourceInfoTransform.nArg
 
@@ -52,7 +79,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
       case KnownWidth(x) => require(x >= n, s"Can't head($n) for width $x < $n")
       case UnknownWidth() =>
     }
-    binop(sourceInfo, UInt(width = n), HeadOp, n)
+    binop(sourceInfo, UInt(Width(n)), HeadOp, n)
   }
 
   /** Returns the specified bit on this wire as a [[Bool]], statically
@@ -67,6 +94,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
     if (isLit()) {
       Bool(((litValue() >> x.toInt) & 1) == 1)
     } else {
+      Binding.checkSynthesizable(this, s"'this' ($this)")
       pushOp(DefPrim(sourceInfo, Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x)))
     }
   }
@@ -108,7 +136,8 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
     if (isLit()) {
       UInt((litValue >> y) & ((BigInt(1) << w) - 1), w)
     } else {
-      pushOp(DefPrim(sourceInfo, UInt(width = w), BitsExtractOp, this.ref, ILit(x), ILit(y)))
+      Binding.checkSynthesizable(this, s"'this' ($this)")
+      pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y)))
     }
   }
 
@@ -118,17 +147,28 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   final def do_apply(x: BigInt, y: BigInt)(implicit sourceInfo: SourceInfo): UInt =
     apply(x.toInt, y.toInt)
 
-  private[Chisel] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T =
+  private[core] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
     pushOp(DefPrim(sourceInfo, dest, op, this.ref))
-  private[Chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T =
+  }
+  private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
     pushOp(DefPrim(sourceInfo, dest, op, this.ref, ILit(other)))
-  private[Chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T =
+  }
+  private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
+    Binding.checkSynthesizable(other, s"'other' ($other)")
     pushOp(DefPrim(sourceInfo, dest, op, this.ref, other.ref))
-
-  private[Chisel] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool =
+  }
+  private[core] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
+    Binding.checkSynthesizable(other, s"'other' ($other)")
     pushOp(DefPrim(sourceInfo, Bool(), op, this.ref, other.ref))
-  private[Chisel] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool =
+  }
+  private[core] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
     pushOp(DefPrim(sourceInfo, Bool(), op, this.ref))
+  }
 
   /** Returns this wire zero padded up to the specified width.
     *
@@ -211,6 +251,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   def do_asSInt(implicit sourceInfo: SourceInfo): SInt
 
   /** Reinterpret cast to Bits. */
+  @deprecated("Use asUInt, which does the same thing but returns a more concrete type", "chisel3")
   final def asBits(): Bits = macro SourceInfoTransform.noArg
 
   def do_asBits(implicit sourceInfo: SourceInfo): Bits = asUInt()
@@ -224,9 +265,9 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
 
   def do_toBool(implicit sourceInfo: SourceInfo): Bool = {
     width match {
-    case KnownWidth(1) => this(0)
-    case _ => throwException(s"can't covert UInt<$width> to Bool")
-  }
+      case KnownWidth(1) => this(0)
+      case _ => throwException(s"can't covert UInt<$width> to Bool")
+    }
   }
 
   /** Returns this wire concatenated with `other`, where this wire forms the
@@ -246,6 +287,9 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
     res := that
     res
   }
+
+  /** Default print as [[Decimal]] */
+  final def toPrintable: Printable = Decimal(this)
 }
 
 /** Provides a set of operations to create UInt types and literals.
@@ -344,19 +388,15 @@ abstract trait Num[T <: Data] {
 /** A data type for unsigned integers, represented as a binary bitvector.
   * Defines arithmetic operations between other integer types.
   */
-sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULit] = None)
-    extends Bits(dir, width, lit) with Num[UInt] {
-  private[Chisel] override def cloneTypeWidth(w: Width): this.type =
-    new UInt(dir, w).asInstanceOf[this.type]
-  private[Chisel] def toType = s"UInt$width"
+sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
+    extends Bits(width, lit) with Num[UInt] {
 
-  override private[Chisel] def fromInt(value: BigInt, width: Int): this.type =
-    UInt(value, width).asInstanceOf[this.type]
+  private[core] override def cloneTypeWidth(w: Width): this.type =
+    new UInt(w).asInstanceOf[this.type]
+  private[chisel3] def toType = s"UInt$width"
 
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: UInt => this connect that
-    case _ => this badConnect that
-  }
+  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
+    UInt(value, width).asInstanceOf[this.type]
 
   // TODO: refactor to share documentation with Num or add independent scaladoc
   final def unary_- (): UInt = macro SourceInfoTransform.noArg
@@ -430,7 +470,7 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
 
   final def unary_! () : Bool = macro SourceInfoTransform.noArg
 
-  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === Bits(0)
+  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === UInt(0, 1)
 
   override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): UInt =
     binop(sourceInfo, UInt(this.width + that), ShiftLeftOp, that)
@@ -470,31 +510,54 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
 }
 
 // This is currently a factory because both Bits and UInt inherit it.
-private[Chisel] sealed trait UIntFactory {
+private[core] sealed trait UIntFactory {
   /** Create a UInt type with inferred width. */
-  def apply(): UInt = apply(NO_DIR, Width())
-  /** Create a UInt type or port with fixed width. */
-  def apply(dir: Direction = NO_DIR, width: Int): UInt = apply(dir, Width(width))
-  /** Create a UInt port with inferred width. */
-  def apply(dir: Direction): UInt = apply(dir, Width())
-
-  /** Create a UInt literal with inferred width. */
-  def apply(value: BigInt): UInt = apply(value, Width())
+  def apply(): UInt = apply(Width())
+  /** Create a UInt port with specified width. */
+  def apply(width: Width): UInt = new UInt(width)
+  /** Create a UInt with a specified width - compatibility with Chisel2. */
+  def width(width: Int): UInt = apply(Width(width))
+  /** Create a UInt port with specified width. */
+  def width(width: Width): UInt = new UInt(width)
   /** Create a UInt literal with fixed width. */
-  def apply(value: BigInt, width: Int): UInt = apply(value, Width(width))
+  def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
   /** Create a UInt literal with inferred width. */
-  def apply(n: String): UInt = apply(parse(n), parsedWidth(n))
-  /** Create a UInt literal with fixed width. */
-  def apply(n: String, width: Int): UInt = apply(parse(n), width)
-
-  /** Create a UInt type with specified width. */
-  def apply(width: Width): UInt = apply(NO_DIR, width)
-  /** Create a UInt port with specified width. */
-  def apply(dir: Direction, width: Width): UInt = new UInt(dir, width)
+  def apply(n: String): UInt = Lit(n)
+   /** Create a UInt literal with fixed width. */
+  def apply(n: String, width: Int): UInt = Lit(parse(n), width)
   /** Create a UInt literal with specified width. */
-  def apply(value: BigInt, width: Width): UInt = {
+  def apply(value: BigInt, width: Width): UInt = Lit(value, width)
+  def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+   /** Create a UInt literal with inferred width. */
+  def Lit(value: BigInt): UInt = Lit(value, Width())
+  def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n))
+   /** Create a UInt literal with fixed width. */
+  def Lit(n: String, width: Int): UInt = Lit(parse(n), width)
+   /** Create a UInt literal with specified width. */
+  def Lit(value: BigInt, width: Width): UInt = {
     val lit = ULit(value, width)
-    new UInt(NO_DIR, lit.width, Some(lit))
+    val result = new UInt(lit.width, Some(lit))
+    // Bind result to being an Literal
+    result.binding = LitBinding()
+    result
+  }
+
+  /** Create a UInt with a specified width - compatibility with Chisel2. */
+  // NOTE: This resolves UInt(width = 32)
+  def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+  /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
+  def apply(value: BigInt): UInt = apply(value, Width())
+  /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+  def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
+  /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
+  def apply(dir: Direction): UInt = apply(dir, Width())
+  def apply(dir: Direction, wWidth: Width): UInt = {
+    val result = apply(wWidth)
+    dir match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
   }
 
   private def parse(n: String) = {
@@ -521,18 +584,14 @@ private[Chisel] sealed trait UIntFactory {
 
 object UInt extends UIntFactory
 
-sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = None)
-    extends Bits(dir, width, lit) with Num[SInt] {
-  private[Chisel] override def cloneTypeWidth(w: Width): this.type =
-    new SInt(dir, w).asInstanceOf[this.type]
-  private[Chisel] def toType = s"SInt$width"
+sealed class SInt private (width: Width, lit: Option[SLit] = None)
+    extends Bits(width, lit) with Num[SInt] {
 
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: SInt => this connect that
-    case _ => this badConnect that
-  }
+  private[core] override def cloneTypeWidth(w: Width): this.type =
+    new SInt(w).asInstanceOf[this.type]
+  private[chisel3] def toType = s"SInt$width"
 
-  override private[Chisel] def fromInt(value: BigInt, width: Int): this.type =
+  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
     SInt(value, width).asInstanceOf[this.type]
 
   final def unary_- (): SInt = macro SourceInfoTransform.noArg
@@ -627,25 +686,46 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
 
 object SInt {
   /** Create an SInt type with inferred width. */
-  def apply(): SInt = apply(NO_DIR, Width())
-  /** Create an SInt type or port with fixed width. */
-  def apply(dir: Direction = NO_DIR, width: Int): SInt = apply(dir, Width(width))
-  /** Create an SInt port with inferred width. */
-  def apply(dir: Direction): SInt = apply(dir, Width())
+  def apply(): SInt = apply(Width())
+  /** Create a SInt type or port with fixed width. */
+  def apply(width: Width): SInt = new SInt(width)
+  /** Create a SInt type or port with fixed width. */
+  def width(width: Int): SInt = apply(Width(width))
+  /** Create an SInt type with specified width. */
+  def width(width: Width): SInt = new SInt(width)
 
   /** Create an SInt literal with inferred width. */
-  def apply(value: BigInt): SInt = apply(value, Width())
+  def apply(value: BigInt): SInt = Lit(value)
   /** Create an SInt literal with fixed width. */
-  def apply(value: BigInt, width: Int): SInt = apply(value, Width(width))
+  def apply(value: BigInt, width: Int): SInt = Lit(value, width)
 
-  /** Create an SInt type with specified width. */
-  def apply(width: Width): SInt = new SInt(NO_DIR, width)
-  /** Create an SInt port with specified width. */
-  def apply(dir: Direction, width: Width): SInt = new SInt(dir, width)
   /** Create an SInt literal with specified width. */
-  def apply(value: BigInt, width: Width): SInt = {
+  def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+
+  def Lit(value: BigInt): SInt = Lit(value, Width())
+  def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
+   /** Create an SInt literal with specified width. */
+  def Lit(value: BigInt, width: Width): SInt = {
+
     val lit = SLit(value, width)
-    new SInt(NO_DIR, lit.width, Some(lit))
+    val result = new SInt(lit.width, Some(lit))
+    // Bind result to being an Literal
+    result.binding = LitBinding()
+    result
+  }
+  /** Create a SInt with a specified width - compatibility with Chisel2. */
+  def apply(dir: Option[Direction] = None, width: Int): SInt = apply(Width(width))
+  /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
+  def apply(dir: Direction, width: Int): SInt = apply(dir, Width(width))
+  /** Create a SInt with a specified direction, but unspecified width - compatibility with Chisel2. */
+  def apply(dir: Direction): SInt = apply(dir, Width())
+  def apply(dir: Direction, wWidth: Width): SInt = {
+    val result = apply(wWidth)
+    dir match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
   }
 }
 
@@ -653,13 +733,13 @@ object SInt {
 // operations on a Bool make sense?
 /** A data type for booleans, defined as a single bit indicating true or false.
   */
-sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Width(1), lit) {
-  private[Chisel] override def cloneTypeWidth(w: Width): this.type = {
+sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) {
+  private[core] override def cloneTypeWidth(w: Width): this.type = {
     require(!w.known || w.get == 1)
-    new Bool(dir).asInstanceOf[this.type]
+    new Bool().asInstanceOf[this.type]
   }
 
-  override private[Chisel] def fromInt(value: BigInt, width: Int): this.type = {
+  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = {
     require((value == 0 || value == 1) && width == 1)
     Bool(value == 1).asInstanceOf[this.type]
   }
@@ -692,16 +772,36 @@ sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Wi
   def && (that: Bool): Bool = macro SourceInfoTransform.thatArg
 
   def do_&& (that: Bool)(implicit sourceInfo: SourceInfo): Bool = this & that
+
+  /** Reinterprets this Bool as a Clock.  */
+  def asClock(): Clock = macro SourceInfoTransform.noArg
+
+  def do_asClock(implicit sourceInfo: SourceInfo): Clock = pushOp(DefPrim(sourceInfo, Clock(), AsClockOp, ref))
 }
 
 object Bool {
   /** Creates an empty Bool.
    */
-  def apply(dir: Direction = NO_DIR): Bool = new Bool(dir)
+  def apply(): Bool = new Bool()
 
   /** Creates Bool literal.
    */
-  def apply(x: Boolean): Bool = new Bool(NO_DIR, Some(ULit(if (x) 1 else 0, Width(1))))
+  def apply(x: Boolean): Bool = Lit(x)
+  def Lit(x: Boolean): Bool = {
+    val result = new Bool(Some(ULit(if (x) 1 else 0, Width(1))))
+    // Bind result to being an Literal
+    result.binding = LitBinding()
+    result
+  }
+  /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+  def apply(dir: Direction): Bool = {
+    val result = apply()
+    dir match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
+  }
 }
 
 object Mux {
@@ -730,14 +830,22 @@ object Mux {
 
   private def doMux[T <: Data](cond: Bool, con: T, alt: T)(implicit sourceInfo: SourceInfo): T = {
     require(con.getClass == alt.getClass, s"can't Mux between ${con.getClass} and ${alt.getClass}")
+    Binding.checkSynthesizable(cond, s"'cond' ($cond)")
+    Binding.checkSynthesizable(con, s"'con' ($con)")
+    Binding.checkSynthesizable(alt, s"'alt' ($alt)")
     val d = alt.cloneTypeWidth(con.width max alt.width)
     pushOp(DefPrim(sourceInfo, d, MultiplexOp, cond.ref, con.ref, alt.ref))
   }
 
+  private[core] def typesCompatible[T <: Data](x: T, y: T): Boolean = {
+    val sameTypes = x.getClass == y.getClass
+    val sameElements = x.flatten zip y.flatten forall { case (a, b) => a.getClass == b.getClass && a.width == b.width }
+    val sameNumElements = x.flatten.size == y.flatten.size
+    sameTypes && sameElements && sameNumElements
+  }
+
   private def doAggregateMux[T <: Data](cond: Bool, con: T, alt: T)(implicit sourceInfo: SourceInfo): T = {
-    require(con.getClass == alt.getClass, s"can't Mux between ${con.getClass} and ${alt.getClass}")
-    for ((c, a) <- con.flatten zip alt.flatten)
-      require(c.width == a.width, "can't Mux between aggregates of different width")
+    require(typesCompatible(con, alt), s"can't Mux between heterogeneous types ${con.getClass} and ${alt.getClass}")
     doMux(cond, con, alt)
   }
 }
diff --git a/chiselFrontend/src/main/scala/Chisel/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index b634f021..c1352566 100644
--- a/chiselFrontend/src/main/scala/Chisel/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -1,10 +1,12 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
-import internal.Builder.pushCommand
-import internal.firrtl.{ModuleIO, DefInvalid}
-import internal.sourceinfo.SourceInfo
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl.{ModuleIO, DefInvalid}
+import chisel3.internal.sourceinfo.SourceInfo
+// TODO: remove this once we have CompileOptions threaded through the macro system.
+import chisel3.core.ExplicitCompileOptions.NotStrict
 
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
@@ -24,23 +26,31 @@ abstract class BlackBox extends Module {
   // The body of a BlackBox is empty, the real logic happens in firrtl/Emitter.scala
   // Bypass standard clock, reset, io port declaration by flattening io
   // TODO(twigg): ? Really, overrides are bad, should extend BaseModule....
-  override private[Chisel] def ports = io.elements.toSeq
+  override private[core] def ports = io.elements.toSeq
 
   // Do not do reflective naming of internal signals, just name io
-  override private[Chisel] def setRefs(): this.type = {
-    for ((name, port) <- ports) {
-      port.setRef(ModuleIO(this, _namespace.name(name)))
-    }
+  override private[core] def setRefs(): this.type = {
     // setRef is not called on the actual io.
     // There is a risk of user improperly attempting to connect directly with io
     // Long term solution will be to define BlackBox IO differently as part of
     //   it not descending from the (current) Module
+    for ((name, port) <- ports) {
+      port.setRef(ModuleIO(this, _namespace.name(name)))
+    }
+    // We need to call forceName and onModuleClose on all of the sub-elements
+    // of the io bundle, but NOT on the io bundle itself.
+    // Doing so would cause the wrong names to be assigned, since their parent
+    // is now the module itself instead of the io bundle.
+    for (id <- _ids; if id ne io) {
+      id.forceName(default="T", _namespace)
+      id._onModuleClose
+    }
     this
   }
 
   // Don't setup clock, reset
   // Cann't invalide io in one bunch, must invalidate each part separately
-  override private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
+  override private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
     case Some(p) => {
       // Just init instance inputs
       for((_,port) <- ports) pushCommand(DefInvalid(sourceInfo, port.ref))
diff --git a/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala
new file mode 100644
index 00000000..4dea39b5
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala
@@ -0,0 +1,57 @@
+// See LICENSE for license details.
+
+package chisel3.core
+
+import scala.language.experimental.macros
+
+trait CompileOptions {
+  // Should Bundle connections require a strict match of fields.
+  // If true and the same fields aren't present in both source and sink, a MissingFieldException,
+  // MissingLeftFieldException, or MissingRightFieldException will be thrown.
+  val connectFieldsMustMatch: Boolean
+  // When creating an object that takes a type argument, the argument must be unbound (a pure type).
+  val declaredTypeMustBeUnbound: Boolean
+  // Module IOs should be wrapped in an IO() to define their bindings before the reset of the module is defined.
+  val requireIOWrap: Boolean
+  // If a connection operator fails, don't try the connection with the operands (source and sink) reversed.
+  val dontTryConnectionsSwapped: Boolean
+  // If connection directionality is not explicit, do not use heuristics to attempt to determine it.
+  val dontAssumeDirectionality: Boolean
+  // Issue a deprecation warning if Data.{flip, asInput,asOutput} is used
+  // instead of Flipped, Input, or Output.
+  val deprecateOldDirectionMethods: Boolean
+  // Check that referenced Data have actually been declared.
+  val checkSynthesizable: Boolean
+}
+
+object CompileOptions {
+  // Provides a low priority Strict default. Can be overridden by importing the NotStrict option.
+  implicit def materialize: CompileOptions = chisel3.core.ExplicitCompileOptions.Strict
+}
+
+object ExplicitCompileOptions {
+  // Collection of "not strict" connection compile options.
+  // These provide compatibility with existing code.
+  // import chisel3.core.ExplicitCompileOptions.NotStrict
+  implicit object NotStrict extends CompileOptions {
+    val connectFieldsMustMatch = false
+    val declaredTypeMustBeUnbound = false
+    val requireIOWrap = false
+    val dontTryConnectionsSwapped = false
+    val dontAssumeDirectionality = false
+    val deprecateOldDirectionMethods = false
+    val checkSynthesizable = false
+  }
+
+  // Collection of "strict" connection compile options, preferred for new code.
+  // import chisel3.core.ExplicitCompileOptions.Strict
+  implicit object Strict extends CompileOptions {
+    val connectFieldsMustMatch = true
+    val declaredTypeMustBeUnbound = true
+    val requireIOWrap = true
+    val dontTryConnectionsSwapped = true
+    val dontAssumeDirectionality = true
+    val deprecateOldDirectionMethods = true
+    val checkSynthesizable = true
+  }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
new file mode 100644
index 00000000..0e473e7e
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -0,0 +1,323 @@
+// See LICENSE for license details.
+
+package chisel3.core
+
+import scala.language.experimental.macros
+
+import chisel3.internal._
+import chisel3.internal.Builder.{pushCommand, pushOp}
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+import chisel3.internal.firrtl.PrimOp.AsUIntOp
+
+sealed abstract class Direction(name: String) {
+  override def toString: String = name
+  def flip: Direction
+}
+object Direction {
+  object Input  extends Direction("input") { override def flip: Direction = Output }
+  object Output extends Direction("output") { override def flip: Direction = Input }
+  object Unspecified extends Direction("unspecified") { override def flip: Direction = Input }
+}
+
+@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
+object debug {  // scalastyle:ignore object.name
+  def apply (arg: Data): Data = arg
+}
+
+object DataMirror {
+  def widthOf(target: Data): Width = target.width
+}
+
+/**
+* Input, Output, and Flipped are used to define the directions of Module IOs.
+*
+* Note that they currently clone their source argument, including its bindings.
+*
+* Thus, an error will be thrown if these are used on bound Data
+*/
+object Input {
+  def apply[T<:Data](source: T): T = {
+    val target = source.chiselCloneType
+    Data.setFirrtlDirection(target, Direction.Input)
+    Binding.bind(target, InputBinder, "Error: Cannot set as input ")
+  }
+}
+object Output {
+  def apply[T<:Data](source: T): T = {
+    val target = source.chiselCloneType
+    Data.setFirrtlDirection(target, Direction.Output)
+    Binding.bind(target, OutputBinder, "Error: Cannot set as output ")
+  }
+}
+object Flipped {
+  def apply[T<:Data](source: T): T = {
+    val target = source.chiselCloneType
+    Data.setFirrtlDirection(target, Data.getFirrtlDirection(source).flip)
+    Binding.bind(target, FlippedBinder, "Error: Cannot flip ")
+  }
+}
+
+object Data {
+  /**
+  * This function returns true if the FIRRTL type of this Data should be flipped
+  * relative to other nodes.
+  *
+  * Note that the current scheme only applies Flip to Elements or Vec chains of
+  * Elements.
+  *
+  * A Bundle is never marked flip, instead preferring its root fields to be marked
+  *
+  * The Vec check is due to the fact that flip must be factored out of the vec, ie:
+  * must have flip field: Vec(UInt) instead of field: Vec(flip UInt)
+  */
+  private[chisel3] def isFlipped(target: Data): Boolean = target match {
+    case (element: Element) => element.binding.direction == Some(Direction.Input)
+    case (vec: Vec[Data @unchecked]) => isFlipped(vec.sample_element)
+    case (bundle: Bundle) => false
+  }
+
+  /** This function returns the "firrtl" flipped-ness for the specified object.
+    *
+    * @param target the object for which we want the "firrtl" flipped-ness.
+    */
+  private[chisel3] def isFirrtlFlipped(target: Data): Boolean = {
+    Data.getFirrtlDirection(target) == Direction.Input
+  }
+
+  /** This function gets the "firrtl" direction for the specified object.
+    *
+    * @param target the object for which we want to get the "firrtl" direction.
+    */
+  private[chisel3] def getFirrtlDirection(target: Data): Direction = target match {
+    case (vec: Vec[Data @unchecked]) => vec.sample_element.firrtlDirection
+    case _ => target.firrtlDirection
+  }
+
+  /** This function sets the "firrtl" direction for the specified object.
+    *
+    * @param target the object for which we want to set the "firrtl" direction.
+    */
+  private[chisel3] def setFirrtlDirection(target: Data, direction: Direction): Unit = target match {
+    case (vec: Vec[Data @unchecked]) => vec.sample_element.firrtlDirection = direction
+    case _ => target.firrtlDirection = direction
+  }
+
+  implicit class AddDirectionToData[T<:Data](val target: T) extends AnyVal {
+    def asInput(implicit opts: CompileOptions): T = {
+      if (opts.deprecateOldDirectionMethods)
+        Builder.deprecated("Input(Data) should be used over Data.asInput")
+      Input(target)
+    }
+    def asOutput(implicit opts: CompileOptions): T = {
+      if (opts.deprecateOldDirectionMethods)
+        Builder.deprecated("Output(Data) should be used over Data.asOutput")
+      Output(target)
+    }
+    def flip()(implicit opts: CompileOptions): T = {
+      if (opts.deprecateOldDirectionMethods)
+        Builder.deprecated("Flipped(Data) should be used over Data.flip")
+      Flipped(target)
+    }
+  }
+}
+
+/** This forms the root of the type system for wire data types. The data value
+  * must be representable as some number (need not be known at Chisel compile
+  * time) of bits, and must have methods to pack / unpack structured data to /
+  * from bits.
+  */
+abstract class Data extends HasId {
+  // Return ALL elements at root of this type.
+  // Contasts with flatten, which returns just Bits
+  private[chisel3] def allElements: Seq[Element]
+
+  private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+    throwException(s"cannot connect ${this} and ${that}")
+  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = {
+    if (connectCompileOptions.checkSynthesizable) {
+      Binding.checkSynthesizable(this, s"'this' ($this)")
+      Binding.checkSynthesizable(that, s"'that' ($that)")
+      try {
+        MonoConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.forcedModule)
+      } catch {
+        case MonoConnect.MonoConnectException(message) =>
+          throwException(
+            s"Connection between sink ($this) and source ($that) failed @$message"
+          )
+      }
+    } else {
+      this legacyConnect that
+    }
+  }
+  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = {
+    if (connectCompileOptions.checkSynthesizable) {
+      Binding.checkSynthesizable(this, s"'this' ($this)")
+      Binding.checkSynthesizable(that, s"'that' ($that)")
+      try {
+        BiConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.forcedModule)
+      } catch {
+        case BiConnect.BiConnectException(message) =>
+          throwException(
+            s"Connection between left ($this) and source ($that) failed @$message"
+          )
+      }
+    } else {
+      this legacyConnect that
+    }
+  }
+  private[chisel3] def lref: Node = Node(this)
+  private[chisel3] def ref: Arg = if (isLit) litArg.get else lref
+  private[core] def cloneTypeWidth(width: Width): this.type
+  private[chisel3] def toType: String
+  private[core] def width: Width
+  private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit
+
+  def cloneType: this.type
+  def chiselCloneType: this.type = {
+    // Call the user-supplied cloneType method
+    val clone = this.cloneType
+    Data.setFirrtlDirection(clone, Data.getFirrtlDirection(this))
+    //TODO(twigg): Do recursively for better error messages
+    for((clone_elem, source_elem) <- clone.allElements zip this.allElements) {
+      clone_elem.binding = UnboundBinding(source_elem.binding.direction)
+    }
+    clone
+  }
+  final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions)
+  final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions)
+  def litArg(): Option[LitArg] = None
+  def litValue(): BigInt = litArg.get.num
+  def isLit(): Boolean = litArg.isDefined
+
+  /** Returns the width, in bits, if currently known.
+    * @throws java.util.NoSuchElementException if the width is not known. */
+  final def getWidth: Int = width.get
+  /** Returns whether the width is currently known. */
+  final def isWidthKnown: Boolean = width.known
+  /** Returns Some(width) if the width is known, else None. */
+  final def widthOption: Option[Int] = if (isWidthKnown) Some(getWidth) else None
+
+  // While this being in the Data API doesn't really make sense (should be in
+  // Aggregate, right?) this is because of an implementation limitation:
+  // cloneWithDirection, which is private and defined here, needs flatten to
+  // set element directionality.
+  // Related: directionality is mutable state. A possible solution for both is
+  // to define directionality relative to the container, but these parent links
+  // currently don't exist (while this information may be available during
+  // FIRRTL emission, it would break directionality querying from Chisel, which
+  // does get used).
+  private[chisel3] def flatten: IndexedSeq[Bits]
+
+  /** Creates an new instance of this type, unpacking the input Bits into
+    * structured data.
+    *
+    * This performs the inverse operation of toBits.
+    *
+    * @note does NOT assign to the object this is called on, instead creates
+    * and returns a NEW object (useful in a clone-and-assign scenario)
+    * @note does NOT check bit widths, may drop bits during assignment
+    * @note what fromBits assigs to must have known widths
+    */
+  def fromBits(that: Bits): this.type = macro SourceInfoTransform.thatArg
+
+  def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = {
+    var i = 0
+    val wire = Wire(this.chiselCloneType)
+    val bits =
+      if (that.width.known && that.width.get >= wire.width.get) {
+        that
+      } else {
+        Wire(that.cloneTypeWidth(wire.width), init = that)
+      }
+    for (x <- wire.flatten) {
+      x := bits(i + x.getWidth-1, i)
+      i += x.getWidth
+    }
+    wire.asInstanceOf[this.type]
+  }
+
+  /** Packs the value of this object as plain Bits.
+    *
+    * This performs the inverse operation of fromBits(Bits).
+    */
+  @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3")
+  def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo)
+
+  /** Reinterpret cast to UInt.
+    *
+    * @note value not guaranteed to be preserved: for example, a SInt of width
+    * 3 and value -1 (0b111) would become an UInt with value 7
+    * @note Aggregates are recursively packed with the first element appearing
+    * in the least-significant bits of the result.
+    */
+  final def asUInt(): UInt = macro SourceInfoTransform.noArg
+
+  def do_asUInt(implicit sourceInfo: SourceInfo): UInt =
+    SeqUtils.do_asUInt(this.flatten)(sourceInfo)
+
+  // firrtlDirection is the direction we report to firrtl.
+  // It maintains the user-specified value (as opposed to the "actual" or applied/propagated value).
+  // NOTE: This should only be used for emitting acceptable firrtl.
+  // The Element.dir should be used for any tests involving direction.
+  private var firrtlDirection: Direction = Direction.Unspecified
+  /** Default pretty printing */
+  def toPrintable: Printable
+}
+
+object Wire {
+  def apply[T <: Data](t: T): T = macro WireTransform.apply[T]
+
+  // No source info since Scala macros don't yet support named / default arguments.
+  def apply[T <: Data](dummy: Int = 0, init: T): T =
+    do_apply(null.asInstanceOf[T], init)(UnlocatableSourceInfo)
+
+  // No source info since Scala macros don't yet support named / default arguments.
+  def apply[T <: Data](t: T, init: T): T =
+    do_apply(t, init)(UnlocatableSourceInfo)
+
+  def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = {
+    val x = Reg.makeType(chisel3.core.ExplicitCompileOptions.NotStrict, t, null.asInstanceOf[T], init)
+
+    // Bind each element of x to being a Wire
+    Binding.bind(x, WireBinder(Builder.forcedModule), "Error: t")
+
+    pushCommand(DefWire(sourceInfo, x))
+    pushCommand(DefInvalid(sourceInfo, x.ref))
+    if (init != null) {
+      Binding.checkSynthesizable(init, s"'init' ($init)")
+      x := init
+    }
+    x
+  }
+}
+
+object Clock {
+  def apply(): Clock = new Clock
+  def apply(dir: Direction): Clock = {
+    val result = apply()
+    dir match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
+  }
+}
+
+// TODO: Document this.
+sealed class Clock extends Element(Width(1)) {
+  def cloneType: this.type = Clock().asInstanceOf[this.type]
+  private[chisel3] override def flatten: IndexedSeq[Bits] = IndexedSeq()
+  private[core] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[chisel3] def toType = "Clock"
+
+  override def connect (that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match {
+    case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions)
+    case _ => super.badConnect(that)(sourceInfo)
+  }
+
+  /** Not really supported */
+  def toPrintable: Printable = PString("CLOCK")
+
+  override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref))
+}
diff --git a/chiselFrontend/src/main/scala/Chisel/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index e34d5499..9cd5a4d8 100644
--- a/chiselFrontend/src/main/scala/Chisel/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -1,13 +1,15 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, MemTransform}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, MemTransform}
+// TODO: remove this once we have CompileOptions threaded through the macro system.
+import chisel3.core.ExplicitCompileOptions.NotStrict
 
 object Mem {
   @deprecated("Mem argument order should be size, t; this will be removed by the official release", "chisel3")
@@ -19,9 +21,11 @@ object Mem {
     * @param t data type of memory element
     */
   def apply[T <: Data](size: Int, t: T): Mem[T] = macro MemTransform.apply[T]
-
   def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo): Mem[T] = {
-    val mt  = t.cloneType
+    val mt  = t.chiselCloneType
+    Binding.bind(mt, NoDirectionBinder, "Error: fresh t")
+    // TODO(twigg): Remove need for this Binding
+
     val mem = new Mem(mt, size)
     pushCommand(DefMemory(sourceInfo, mem, mt, size)) // TODO multi-clock
     mem
@@ -34,7 +38,10 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
   /** Creates a read accessor into the memory with static addressing. See the
     * class documentation of the memory for more detailed information.
     */
-  def apply(idx: Int): T = apply(UInt(idx))
+  def apply(idx: Int): T = {
+    require(idx >= 0 && idx < length)
+    apply(UInt(idx))
+  }
 
   /** Creates a read/write accessor into the memory with dynamic addressing.
     * See the class documentation of the memory for more detailed information.
@@ -60,7 +67,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
     *
     * @param idx memory element index to write into
     * @param data new data to write
-    * @param mask write mask as a Vec of Bool: a write to the Vec element in
+    * @param mask write mask as a Seq of Bool: a write to the Vec element in
     * memory is only performed if the corresponding mask index is true.
     *
     * @note this is only allowed if the memory's element data type is a Vec
@@ -79,9 +86,18 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
       when (cond) { port := datum }
   }
 
-  private def makePort(sourceInfo: SourceInfo, idx: UInt, dir: MemPortDirection): T =
-    pushCommand(DefMemPort(sourceInfo,
-        t.cloneType, Node(this), dir, idx.ref, Node(idx._parent.get.clock))).id
+  private def makePort(sourceInfo: SourceInfo, idx: UInt, dir: MemPortDirection): T = {
+    Binding.checkSynthesizable(idx, s"'idx' ($idx)")
+    val i = Vec.truncateIndex(idx, length)(sourceInfo)
+
+    val port = pushCommand(
+      DefMemPort(sourceInfo,
+       t.chiselCloneType, Node(this), dir, i.ref, Node(i._parent.get.clock))
+    ).id
+    // Bind each element of port to being a MemoryPort
+    Binding.bind(port, MemoryPortBinder(Builder.forcedModule), "Error: Fresh t")
+    port
+  }
 }
 
 /** A combinational-read, sequential-write memory.
@@ -107,7 +123,10 @@ object SeqMem {
   def apply[T <: Data](size: Int, t: T): SeqMem[T] = macro MemTransform.apply[T]
 
   def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo): SeqMem[T] = {
-    val mt  = t.cloneType
+    val mt  = t.chiselCloneType
+    Binding.bind(mt, NoDirectionBinder, "Error: fresh t")
+    // TODO(twigg): Remove need for this Binding
+
     val mem = new SeqMem(mt, size)
     pushCommand(DefSeqMemory(sourceInfo, mem, mt, size)) // TODO multi-clock
     mem
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
new file mode 100644
index 00000000..55522b4a
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -0,0 +1,211 @@
+// See LICENSE for license details.
+
+package chisel3.core
+
+import scala.collection.mutable.ArrayBuffer
+import scala.language.experimental.macros
+import chisel3.internal._
+import chisel3.internal.Builder._
+import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.{Command => _, _}
+import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
+
+object Module {
+  /** A wrapper method that all Module instantiations must be wrapped in
+    * (necessary to help Chisel track internal state).
+    *
+    * @param m the Module being created
+    *
+    * @return the input module `m` with Chisel metadata properly set
+    */
+  def apply[T <: Module](bc: => T): T = macro InstTransform.apply[T]
+
+  def do_apply[T <: Module](bc: => T)(implicit sourceInfo: SourceInfo): T = {
+    // Don't generate source info referencing parents inside a module, sincce this interferes with
+    // module de-duplication in FIRRTL emission.
+    val childSourceInfo = UnlocatableSourceInfo
+
+    val parent: Option[Module] = Builder.currentModule
+    val m = bc.setRefs() // This will set currentModule!
+    m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs
+    Builder.currentModule = parent // Back to parent!
+    val ports = m.computePorts
+    val component = Component(m, m.name, ports, m._commands)
+    m._component = Some(component)
+    Builder.components += component
+    // Avoid referencing 'parent' in top module
+    if(!Builder.currentModule.isEmpty) {
+      pushCommand(DefInstance(sourceInfo, m, ports))
+      m.setupInParent(childSourceInfo)
+    }
+    m
+  }
+}
+
+/** Abstract base class for Modules, which behave much like Verilog modules.
+  * These may contain both logic and state which are written in the Module
+  * body (constructor).
+  *
+  * @note Module instantiations must be wrapped in a Module() call.
+  */
+abstract class Module(
+  override_clock: Option[Clock]=None, override_reset: Option[Bool]=None)
+                     (implicit moduleCompileOptions: CompileOptions)
+extends HasId {
+  // _clock and _reset can be clock and reset in these 2ary constructors
+  // once chisel2 compatibility issues are resolved
+  def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions)
+  def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions)  = this(None, Option(_reset))(moduleCompileOptions)
+  def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions)
+
+  // This function binds the iodef as a port in the hardware graph
+  private[chisel3] def Port[T<:Data](iodef: T): iodef.type = {
+    // Bind each element of the iodef to being a Port
+    Binding.bind(iodef, PortBinder(this), "Error: iodef")
+    iodef
+  }
+
+  private[core] var ioDefined: Boolean = false
+
+  /**
+   * This must wrap the datatype used to set the io field of any Module.
+   * i.e. All concrete modules must have defined io in this form:
+   * [lazy] val io[: io type] = IO(...[: io type])
+   *
+   * Items in [] are optional.
+   *
+   * The granted iodef WILL NOT be cloned (to allow for more seamless use of
+   * anonymous Bundles in the IO) and thus CANNOT have been bound to any logic.
+   * This will error if any node is bound (e.g. due to logic in a Bundle
+   * constructor, which is considered improper).
+   *
+   * TODO(twigg): Specifically walk the Data definition to call out which nodes
+   * are problematic.
+   */
+  def IO[T<:Data](iodef: T): iodef.type = {
+    require(!ioDefined, "Another IO definition for this module was already declared!")
+    ioDefined = true
+
+    Port(iodef)
+  }
+
+  private[core] val _namespace = Builder.globalNamespace.child
+  private[chisel3] val _commands = ArrayBuffer[Command]()
+  private[core] val _ids = ArrayBuffer[HasId]()
+  Builder.currentModule = Some(this)
+
+  /** Desired name of this module. */
+  def desiredName = this.getClass.getName.split('.').last
+
+  /** Legalized name of this module. */
+  final val name = Builder.globalNamespace.name(desiredName)
+
+  /** FIRRTL Module name */
+  private var _modName: Option[String] = None
+  private[chisel3] def setModName(name: String) = _modName = Some(name)
+  def modName = _modName match {
+    case Some(name) => name
+    case None => throwException("modName should be called after circuit elaboration")
+  }
+
+  /** Keep component for signal names */
+  private[chisel3] var _component: Option[Component] = None
+
+
+  /** Signal name (for simulation). */
+  override def instanceName =
+    if (_parent == None) name else _component match {
+      case None => getRef.name
+      case Some(c) => getRef fullName c
+    }
+
+  /** IO for this Module. At the Scala level (pre-FIRRTL transformations),
+    * connections in and out of a Module may only go through `io` elements.
+    */
+  def io: Bundle
+  val clock = Port(Input(Clock()))
+  val reset = Port(Input(Bool()))
+
+  private[chisel3] def addId(d: HasId) { _ids += d }
+
+  private[core] def ports: Seq[(String,Data)] = Vector(
+    ("clock", clock), ("reset", reset), ("io", io)
+  )
+
+  private[core] def computePorts: Seq[firrtl.Port] = {
+    // If we're auto-wrapping IO definitions, do so now.
+    if (!(compileOptions.requireIOWrap || ioDefined)) {
+      IO(io)
+    }
+    for ((name, port) <- ports) yield {
+      // Port definitions need to know input or output at top-level.
+      // By FIRRTL semantics, 'flipped' becomes an Input
+      val direction = if(Data.isFirrtlFlipped(port)) Direction.Input else Direction.Output
+      firrtl.Port(port, direction)
+    }
+  }
+
+  private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
+    _parent match {
+      case Some(p) => {
+        pushCommand(DefInvalid(sourceInfo, io.ref)) // init instance inputs
+        clock := override_clock.getOrElse(p.clock)
+        reset := override_reset.getOrElse(p.reset)
+        this
+      }
+      case None => this
+    }
+  }
+
+  private[core] def setRefs(): this.type = {
+    for ((name, port) <- ports) {
+      port.setRef(ModuleIO(this, _namespace.name(name)))
+    }
+
+    // Suggest names to nodes using runtime reflection
+    def getValNames(c: Class[_]): Set[String] = {
+      if (c == classOf[Module]) Set()
+      else getValNames(c.getSuperclass) ++ c.getDeclaredFields.map(_.getName)
+    }
+    val valNames = getValNames(this.getClass)
+    def isPublicVal(m: java.lang.reflect.Method) =
+      m.getParameterTypes.isEmpty && valNames.contains(m.getName)
+
+    /** Recursively suggests names to supported "container" classes
+      * Arbitrary nestings of supported classes are allowed so long as the
+      * innermost element is of type HasId
+      * Currently supported:
+      *   - Iterable
+      *   - Option
+      * (Note that Map is Iterable[Tuple2[_,_]] and thus excluded)
+      */
+    def nameRecursively(prefix: String, nameMe: Any): Unit =
+      nameMe match {
+        case (id: HasId) => id.suggestName(prefix)
+        case Some(elt) => nameRecursively(prefix, elt)
+        case (iter: Iterable[_]) if iter.hasDefiniteSize =>
+          for ((elt, i) <- iter.zipWithIndex) {
+            nameRecursively(s"${prefix}_${i}", elt)
+          }
+        case _ => // Do nothing
+      }
+    val methods = getClass.getMethods.sortWith(_.getName > _.getName)
+    for (m <- methods if isPublicVal(m)) {
+      nameRecursively(m.getName, m.invoke(this))
+    }
+
+    // For Module instances we haven't named, suggest the name of the Module
+    _ids foreach {
+      case m: Module => m.suggestName(m.name)
+      case _ =>
+    }
+
+    // All suggestions are in, force names to every node.
+    _ids.foreach(_.forceName(default="T", _namespace))
+    _ids.foreach(_._onModuleClose)
+    this
+  }
+  // For debuggers/testers
+  lazy val getPorts = computePorts
+  val compileOptions = moduleCompileOptions
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
new file mode 100644
index 00000000..fcb14e6f
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
@@ -0,0 +1,191 @@
+// See LICENSE for license details.
+
+package chisel3.core
+
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl.Connect
+import scala.language.experimental.macros
+import chisel3.internal.sourceinfo.{DeprecatedSourceInfo, SourceInfo, SourceInfoTransform, UnlocatableSourceInfo, WireTransform}
+
+/**
+* MonoConnect.connect executes a mono-directional connection element-wise.
+*
+* Note that this isn't commutative. There is an explicit source and sink
+* already determined before this function is called.
+*
+* The connect operation will recurse down the left Data (with the right Data).
+* An exception will be thrown if a movement through the left cannot be matched
+* in the right. The right side is allowed to have extra Bundle fields.
+* Vecs must still be exactly the same size.
+*
+* See elemConnect for details on how the root connections are issued.
+*
+* Note that a valid sink must be writable so, one of these must hold:
+* - Is an internal writable node (Reg or Wire)
+* - Is an output of the current module
+* - Is an input of a submodule of the current module
+*
+* Note that a valid source must be readable so, one of these must hold:
+* - Is an internal readable node (Reg, Wire, Op)
+* - Is a literal
+* - Is a port of the current module or submodule of the current module
+*/
+
+object MonoConnect {
+  // These are all the possible exceptions that can be thrown.
+  case class MonoConnectException(message: String) extends Exception(message)
+  // These are from element-level connection
+  def UnreadableSourceException =
+    MonoConnectException(": Source is unreadable from current module.")
+  def UnwritableSinkException =
+    MonoConnectException(": Sink is unwriteable by current module.")
+  def UnknownRelationException =
+    MonoConnectException(": Sink or source unavailable to current module.")
+  // These are when recursing down aggregate types
+  def MismatchedVecException =
+    MonoConnectException(": Sink and Source are different length Vecs.")
+  def MissingFieldException(field: String) =
+    MonoConnectException(s": Source Bundle missing field ($field).")
+  def MismatchedException(sink: String, source: String) =
+    MonoConnectException(s": Sink ($sink) and Source ($source) have different types.")
+
+  /** This function is what recursively tries to connect a sink and source together
+  *
+  * There is some cleverness in the use of internal try-catch to catch exceptions
+  * during the recursive decent and then rethrow them with extra information added.
+  * This gives the user a 'path' to where in the connections things went wrong.
+  */
+  def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Data, source: Data, context_mod: Module): Unit =
+    (sink, source) match {
+      // Handle element case (root case)
+      case (sink_e: Element, source_e: Element) => {
+        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        // TODO(twigg): Verify the element-level classes are connectable
+      }
+      // Handle Vec case
+      case (sink_v: Vec[Data @unchecked], source_v: Vec[Data @unchecked]) => {
+        if(sink_v.length != source_v.length) { throw MismatchedVecException }
+        for(idx <- 0 until sink_v.length) {
+          try {
+            connect(sourceInfo, connectCompileOptions, sink_v(idx), source_v(idx), context_mod)
+          } catch {
+            case MonoConnectException(message) => throw MonoConnectException(s"($idx)$message")
+          }
+        }
+      }
+      // Handle Bundle case
+      case (sink_b: Bundle, source_b: Bundle) => {
+        // For each field, descend with right
+        for((field, sink_sub) <- sink_b.elements) {
+          try {
+            source_b.elements.get(field) match {
+              case Some(source_sub) => connect(sourceInfo, connectCompileOptions, sink_sub, source_sub, context_mod)
+              case None => {
+                if (connectCompileOptions.connectFieldsMustMatch) {
+                  throw MissingFieldException(field)
+                }
+              }
+            }
+          } catch {
+            case MonoConnectException(message) => throw MonoConnectException(s".$field$message")
+          }
+        }
+      }
+      // Sink and source are different subtypes of data so fail
+      case (sink, source) => throw MismatchedException(sink.toString, source.toString)
+    }
+
+  // This function (finally) issues the connection operation
+  private def issueConnect(sink: Element, source: Element)(implicit sourceInfo: SourceInfo): Unit = {
+    pushCommand(Connect(sourceInfo, sink.lref, source.ref))
+  }
+
+  // This function checks if element-level connection operation allowed.
+  // Then it either issues it or throws the appropriate exception.
+  def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: Module): Unit = {
+    import Direction.{Input, Output} // Using extensively so import these
+    // If source has no location, assume in context module
+    // This can occur if is a literal, unbound will error previously
+    val sink_mod: Module   = sink.binding.location.getOrElse(throw UnwritableSinkException)
+    val source_mod: Module = source.binding.location.getOrElse(context_mod)
+
+    val sink_direction: Option[Direction] = sink.binding.direction
+    val source_direction: Option[Direction] = source.binding.direction
+    // None means internal
+
+    // CASE: Context is same module that both left node and right node are in
+    if( (context_mod == sink_mod) && (context_mod == source_mod) ) {
+      ((sink_direction, source_direction): @unchecked) match {
+        //    SINK          SOURCE
+        //    CURRENT MOD   CURRENT MOD
+        case (Some(Output), _) => issueConnect(sink, source)
+        case (None,         _) => issueConnect(sink, source)
+        case (Some(Input),  _) => throw UnwritableSinkException
+      }
+    }
+
+    // CASE: Context is same module as sink node and right node is in a child module
+    else if( (sink_mod == context_mod) &&
+             (source_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, right node better be a port node and thus have a direction
+      ((sink_direction, source_direction): @unchecked) match {
+        //    SINK          SOURCE
+        //    CURRENT MOD   CHILD MOD
+        case (None,         Some(Output)) => issueConnect(sink, source)
+        case (None,         Some(Input))  => issueConnect(sink, source)
+        case (Some(Output), Some(Output)) => issueConnect(sink, source)
+        case (Some(Output), Some(Input))  => issueConnect(sink, source)
+        case (_,            None) => {
+          if (!(connectCompileOptions.dontAssumeDirectionality)) {
+            issueConnect(sink, source)
+          } else {
+            throw UnreadableSourceException
+          }
+        }
+        case (Some(Input),  Some(Output)) if (!(connectCompileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink)
+        case (Some(Input),  _)    => throw UnwritableSinkException
+      }
+    }
+
+    // CASE: Context is same module as source node and sink node is in child module
+    else if( (source_mod == context_mod) &&
+             (sink_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, left node better be a port node and thus have a direction
+      ((sink_direction, source_direction): @unchecked) match {
+        //    SINK          SOURCE
+        //    CHILD MOD     CURRENT MOD
+        case (Some(Input),  _) => issueConnect(sink, source)
+        case (Some(Output), _) => throw UnwritableSinkException
+        case (None,         _) => throw UnwritableSinkException
+      }
+    }
+
+    // CASE: Context is the parent module of both the module containing sink node
+    //                                        and the module containing source node
+    //   Note: This includes case when sink and source in same module but in parent
+    else if( (sink_mod._parent.map(_ == context_mod).getOrElse(false)) &&
+             (source_mod._parent.map(_ == context_mod).getOrElse(false))
+    ) {
+      // Thus both nodes must be ports and have a direction
+      ((sink_direction, source_direction): @unchecked) match {
+        //    SINK          SOURCE
+        //    CHILD MOD     CHILD MOD
+        case (Some(Input),  Some(Input))  => issueConnect(sink, source)
+        case (Some(Input),  Some(Output)) => issueConnect(sink, source)
+        case (Some(Output), _)            => throw UnwritableSinkException
+        case (_,            None) => {
+          if (!(connectCompileOptions.dontAssumeDirectionality)) {
+            issueConnect(sink, source)
+          } else {
+            throw UnreadableSourceException
+          }
+        }
+        case (None,         _)            => throw UnwritableSinkException
+      }
+    }
+
+    // Not quite sure where left and right are compared to current module
+    // so just error out
+    else throw UnknownRelationException
+  }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printable.scala b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala
new file mode 100644
index 00000000..f6e63936
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala
@@ -0,0 +1,152 @@
+// See LICENSE for license details.
+
+package chisel3.core
+
+import chisel3.internal.firrtl.Component
+import chisel3.internal.HasId
+
+import scala.collection.mutable
+
+import java.util.{
+  MissingFormatArgumentException,
+  UnknownFormatConversionException
+}
+
+/** Superclass of things that can be printed in the resulting circuit
+  *
+  * Usually created using the custom string interpolator p"..."
+  * TODO Add support for names of Modules
+  *   Currently impossible because unpack is called before the name is selected
+  *   Could be implemented by adding a new format specifier to Firrtl (eg. %m)
+  * TODO Should we provide more functions like map and mkPrintable?
+  */
+sealed abstract class Printable {
+  /** Unpack into format String and a List of String arguments (identifiers)
+    * @note This must be called after elaboration when Chisel nodes actually
+    *   have names
+    */
+  def unpack(ctx: Component): (String, Iterable[String])
+  /** Allow for appending Printables like Strings */
+  final def +(that: Printable) = Printables(List(this, that))
+  /** Allow for appending Strings to Printables */
+  final def +(that: String) = Printables(List(this, PString(that)))
+}
+object Printable {
+  /** Pack standard printf fmt, args* style into Printable
+    */
+  def pack(fmt: String, data: Data*): Printable = {
+    val args = data.toIterator
+
+    // Error handling
+    def carrotAt(index: Int) = (" " * index) + "^"
+    def errorMsg(index: Int) =
+      s"""|    fmt = "$fmt"
+          |           ${carrotAt(index)}
+          |    data = ${data mkString ", "}""".stripMargin
+    def getArg(i: Int): Data = {
+      if (!args.hasNext) {
+        val msg = "has no matching argument!\n" + errorMsg(i)
+          // Exception wraps msg in s"Format Specifier '$msg'"
+        throw new MissingFormatArgumentException(msg)
+      }
+      args.next()
+    }
+
+    val pables = mutable.ListBuffer.empty[Printable]
+    var str = ""
+    var percent = false
+    for ((c, i) <- fmt.zipWithIndex) {
+      if (percent) {
+        val arg = c match {
+          case FirrtlFormat(x) => FirrtlFormat(x.toString, getArg(i))
+          case 'n' => Name(getArg(i))
+          case 'N' => FullName(getArg(i))
+          case '%' => Percent
+          case x =>
+            val msg = s"Illegal format specifier '$x'!\n" + errorMsg(i)
+            throw new UnknownFormatConversionException(msg)
+        }
+        pables += PString(str dropRight 1) // remove format %
+        pables += arg
+        str = ""
+        percent = false
+      } else {
+        str += c
+        percent = c == '%'
+      }
+    }
+    if (percent) {
+      val msg = s"Trailing %\n" + errorMsg(fmt.size - 1)
+      throw new UnknownFormatConversionException(msg)
+    }
+    require(!args.hasNext,
+      s"Too many arguments! More format specifier(s) expected!\n" +
+      errorMsg(fmt.size))
+
+    pables += PString(str)
+    Printables(pables)
+  }
+}
+
+case class Printables(pables: Iterable[Printable]) extends Printable {
+  require(pables.hasDefiniteSize, "Infinite-sized iterables are not supported!")
+  final def unpack(ctx: Component): (String, Iterable[String]) = {
+    val (fmts, args) = pables.map(_ unpack ctx).unzip
+    (fmts.mkString, args.flatten)
+  }
+}
+/** Wrapper for printing Scala Strings */
+case class PString(str: String) extends Printable {
+  final def unpack(ctx: Component): (String, Iterable[String]) =
+    (str replaceAll ("%", "%%"), List.empty)
+}
+/** Superclass for Firrtl format specifiers for Bits */
+sealed abstract class FirrtlFormat(specifier: Char) extends Printable {
+  def bits: Bits
+  def unpack(ctx: Component): (String, Iterable[String]) = {
+    (s"%$specifier", List(bits.ref.fullName(ctx)))
+  }
+}
+object FirrtlFormat {
+  final val legalSpecifiers = List('d', 'x', 'b', 'c')
+
+  def unapply(x: Char): Option[Char] =
+    Option(x) filter (x => legalSpecifiers contains x)
+
+  /** Helper for constructing Firrtl Formats
+    * Accepts data to simplify pack
+    */
+  def apply(specifier: String, data: Data): FirrtlFormat = {
+    val bits = data match {
+      case b: Bits => b
+      case d => throw new Exception(s"Trying to construct FirrtlFormat with non-bits $d!")
+    }
+    specifier match {
+      case "d" => Decimal(bits)
+      case "x" => Hexadecimal(bits)
+      case "b" => Binary(bits)
+      case "c" => Character(bits)
+      case c => throw new Exception(s"Illegal format specifier '$c'!")
+    }
+  }
+}
+/** Format bits as Decimal */
+case class Decimal(bits: Bits) extends FirrtlFormat('d')
+/** Format bits as Hexidecimal */
+case class Hexadecimal(bits: Bits) extends FirrtlFormat('x')
+/** Format bits as Binary */
+case class Binary(bits: Bits) extends FirrtlFormat('b')
+/** Format bits as Character */
+case class Character(bits: Bits) extends FirrtlFormat('c')
+/** Put innermost name (eg. field of bundle) */
+case class Name(data: Data) extends Printable {
+  final def unpack(ctx: Component): (String, Iterable[String]) = (data.ref.name, List.empty)
+}
+/** Put full name within parent namespace (eg. bundleName.field) */
+case class FullName(data: Data) extends Printable {
+  final def unpack(ctx: Component): (String, Iterable[String]) = (data.ref.fullName(ctx), List.empty)
+}
+/** Represents escaped percents */
+case object Percent extends Printable {
+  final def unpack(ctx: Component): (String, Iterable[String]) = ("%%", List.empty)
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
new file mode 100644
index 00000000..4ec13751
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
@@ -0,0 +1,70 @@
+// See LICENSE for license details.
+
+package chisel3.core
+
+import scala.language.experimental.macros
+
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.SourceInfo
+
+object printf { // scalastyle:ignore object.name
+  /** Helper for packing escape characters */
+  private[chisel3] def format(formatIn: String): String = {
+    require(formatIn forall (c => c.toInt > 0 && c.toInt < 128),
+      "format strings must comprise non-null ASCII values")
+    def escaped(x: Char) = {
+      require(x.toInt >= 0)
+      if (x == '"' || x == '\\') {
+        s"\\${x}"
+      } else if (x == '\n') {
+        "\\n"
+      } else {
+        require(x.toInt >= 32) // TODO \xNN once FIRRTL issue #59 is resolved
+        x
+      }
+    }
+    formatIn map escaped mkString ""
+  }
+
+  /** Prints a message in simulation.
+    *
+    * Does not fire when in reset (defined as the encapsulating Module's
+    * reset). If your definition of reset is not the encapsulating Module's
+    * reset, you will need to gate this externally.
+    *
+    * May be called outside of a Module (like defined in a function), so
+    * functions using printf make the standard Module assumptions (single clock
+    * and single reset).
+    *
+    * @param fmt printf format string
+    * @param data format string varargs containing data to print
+    */
+  def apply(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo): Unit =
+    apply(Printable.pack(fmt, data:_*))
+  /** Prints a message in simulation.
+    *
+    * Does not fire when in reset (defined as the encapsulating Module's
+    * reset). If your definition of reset is not the encapsulating Module's
+    * reset, you will need to gate this externally.
+    *
+    * May be called outside of a Module (like defined in a function), so
+    * functions using printf make the standard Module assumptions (single clock
+    * and single reset).
+    *
+    * @param pable [[Printable]] to print
+    */
+  def apply(pable: Printable)(implicit sourceInfo: SourceInfo): Unit = {
+    when (!Builder.forcedModule.reset) {
+      printfWithoutReset(pable)
+    }
+  }
+
+  private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo): Unit = {
+    val clock = Builder.forcedModule.clock
+    pushCommand(Printf(sourceInfo, Node(clock), pable))
+  }
+  private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo): Unit =
+    printfWithoutReset(Printable.pack(fmt, data:_*))
+}
diff --git a/chiselFrontend/src/main/scala/Chisel/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index c8faa5c9..9d380695 100644
--- a/chiselFrontend/src/main/scala/Chisel/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -1,22 +1,25 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
 
 object Reg {
-  private[Chisel] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = {
+  private[core] def makeType[T <: Data](compileOptions: CompileOptions, t: T = null, next: T = null, init: T = null): T = {
     if (t ne null) {
-      t.cloneType
+      if (compileOptions.declaredTypeMustBeUnbound) {
+        Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using cloneType?")
+      }
+      t.chiselCloneType
     } else if (next ne null) {
       next.cloneTypeWidth(Width())
     } else if (init ne null) {
       init.litArg match {
         // For e.g. Reg(init=UInt(0, k)), fix the Reg's width to k
-        case Some(lit) if lit.forcedWidth => init.cloneType
+        case Some(lit) if lit.forcedWidth => init.chiselCloneType
         case _ => init.cloneTypeWidth(Width())
       }
     } else {
@@ -37,18 +40,18 @@ object Reg {
     * is a valid value. In those cases, you can either use the outType only Reg
     * constructor or pass in `null.asInstanceOf[T]`.
     */
-  def apply[T <: Data](t: T = null, next: T = null, init: T = null): T =
+  def apply[T <: Data](t: T = null, next: T = null, init: T = null)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T =
     // Scala macros can't (yet) handle named or default arguments.
-    do_apply(t, next, init)(UnlocatableSourceInfo)
+    do_apply(t, next, init)(sourceInfo, compileOptions)
 
   /** Creates a register without initialization (reset is ignored). Value does
     * not change unless assigned to (using the := operator).
     *
     * @param outType: data type for the register
     */
-  def apply[T <: Data](outType: T): T = Reg[T](outType, null.asInstanceOf[T], null.asInstanceOf[T])
+  def apply[T <: Data](outType: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = Reg[T](outType, null.asInstanceOf[T], null.asInstanceOf[T])(sourceInfo, compileOptions)
 
-  def do_apply[T <: Data](t: T, next: T, init: T)(implicit sourceInfo: SourceInfo): T = {
+  def do_apply[T <: Data](t: T, next: T, init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict): T = {
     // TODO: write this in a way that doesn't need nulls (bad Scala style),
     // null.asInstanceOf[T], and two constructors. Using Option types are an
     // option, but introduces cumbersome syntax (wrap everything in a Some()).
@@ -56,14 +59,20 @@ object Reg {
     // but Scala's type inferencer and implicit insertion isn't smart enough
     // to resolve all use cases. If the type inferencer / implicit resolution
     // system improves, this may be changed.
-    val x = makeType(t, next, init)
+    val x = makeType(compileOptions, t, next, init)
     val clock = Node(x._parent.get.clock) // TODO multi-clock
+
+    // Bind each element of x to being a Reg
+    Binding.bind(x, RegBinder(Builder.forcedModule), "Error: t")
+
     if (init == null) {
       pushCommand(DefReg(sourceInfo, x, clock))
     } else {
+      Binding.checkSynthesizable(init, s"'init' ($init)")
       pushCommand(DefRegInit(sourceInfo, x, clock, Node(x._parent.get.reset), init.ref))
     }
     if (next != null) {
+      Binding.checkSynthesizable(next, s"'next' ($next)")
       x := next
     }
     x
diff --git a/chiselFrontend/src/main/scala/Chisel/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index 9a15fd5f..0d8604cd 100644
--- a/chiselFrontend/src/main/scala/Chisel/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -1,13 +1,18 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
-private[Chisel] object SeqUtils {
-  /** Equivalent to Cat(r(n-1), ..., r(0)) */
+private[chisel3] object SeqUtils {
+  /** Concatenates the data elements of the input sequence, in sequence order, together.
+    * The first element of the sequence forms the least significant bits, while the last element
+    * in the sequence forms the most significant bits.
+    *
+    * Equivalent to r(n-1) ## ... ## r(1) ## r(0).
+    */
   def asUInt[T <: Bits](in: Seq[T]): UInt = macro SourceInfoTransform.inArg
 
   def do_asUInt[T <: Bits](in: Seq[T])(implicit sourceInfo: SourceInfo): UInt = {
@@ -20,20 +25,18 @@ private[Chisel] object SeqUtils {
     }
   }
 
-  /** Counts the number of true Bools in a Seq */
+  /** Outputs the number of elements that === Bool(true).
+    */
   def count(in: Seq[Bool]): UInt = macro SourceInfoTransform.inArg
 
-  def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo): UInt = {
-    if (in.size == 0) {
-      UInt(0)
-    } else if (in.size == 1) {
-      in.head
-    } else {
-      count(in.slice(0, in.size/2)) + (UInt(0) ## count(in.slice(in.size/2, in.size)))
-    }
+  def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo): UInt = in.size match {
+    case 0 => UInt(0)
+    case 1 => in.head
+    case n => count(in take n/2) +& count(in drop n/2)
   }
 
-  /** Returns data value corresponding to first true predicate */
+  /** Returns the data value corresponding to the first true predicate.
+    */
   def priorityMux[T <: Data](in: Seq[(Bool, T)]): T = macro SourceInfoTransform.inArg
 
   def do_priorityMux[T <: Data](in: Seq[(Bool, T)])(implicit sourceInfo: SourceInfo): T = {
@@ -44,14 +47,17 @@ private[Chisel] object SeqUtils {
     }
   }
 
-  /** Returns data value corresponding to lone true predicate */
+  /** Returns the data value corresponding to the lone true predicate.
+    *
+    * @note assumes exactly one true predicate, results undefined otherwise
+    */
   def oneHotMux[T <: Data](in: Iterable[(Bool, T)]): T = macro SourceInfoTransform.inArg
 
   def do_oneHotMux[T <: Data](in: Iterable[(Bool, T)])(implicit sourceInfo: SourceInfo): T = {
     if (in.tail.isEmpty) {
       in.head._2
     } else {
-      val masked = for ((s, i) <- in) yield Mux(s, i.toBits, Bits(0))
+      val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, UInt(0))
       val width = in.map(_._2.width).reduce(_ max _)
       in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_))
     }
diff --git a/chiselFrontend/src/main/scala/Chisel/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala
index 90b3d1a5..196e7903 100644
--- a/chiselFrontend/src/main/scala/Chisel/When.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo}
 
 object when {  // scalastyle:ignore object.name
   /** Create a `when` condition block, where whether a block of logic is
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
new file mode 100644
index 00000000..12cc840e
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -0,0 +1,190 @@
+// See LICENSE for license details.
+
+package chisel3.internal
+
+import scala.util.DynamicVariable
+import scala.collection.mutable.{ArrayBuffer, HashMap}
+
+import chisel3._
+import core._
+import firrtl._
+
+private[chisel3] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
+  private val names = collection.mutable.HashMap[String, Long]()
+  for (keyword <- keywords)
+    names(keyword) = 1
+
+  private def rename(n: String): String = {
+    val index = names.getOrElse(n, 1L)
+    val tryName = s"${n}_${index}"
+    names(n) = index + 1
+    if (this contains tryName) rename(n) else tryName
+  }
+
+  private def sanitize(s: String): String = {
+    // TODO what character set does FIRRTL truly support? using ANSI C for now
+    def legalStart(c: Char) = (c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') || c == '_'
+    def legal(c: Char) = legalStart(c) || (c >= '0' && c <= '9')
+    val res = s filter legal
+    if (res.isEmpty || !legalStart(res.head)) s"_$res" else res
+  }
+
+  def contains(elem: String): Boolean = {
+    names.contains(elem) || parent.map(_ contains elem).getOrElse(false)
+  }
+
+  def name(elem: String): String = {
+    val sanitized = sanitize(elem)
+    if (this contains sanitized) {
+      name(rename(sanitized))
+    } else {
+      names(sanitized) = 1
+      sanitized
+    }
+  }
+
+  def child(kws: Set[String]): Namespace = new Namespace(Some(this), kws)
+  def child: Namespace = child(Set())
+}
+
+private[chisel3] class IdGen {
+  private var counter = -1L
+  def next: Long = {
+    counter += 1
+    counter
+  }
+}
+
+/** Public API to access Node/Signal names.
+  * currently, the node's name, the full path name, and references to its parent Module and component.
+  * These are only valid once the design has been elaborated, and should not be used during its construction.
+  */
+trait InstanceId {
+  def instanceName: String
+  def pathName: String
+  def parentPathName: String
+  def parentModName: String
+}
+
+private[chisel3] trait HasId extends InstanceId {
+  private[chisel3] def _onModuleClose: Unit = {} // scalastyle:ignore method.name
+  private[chisel3] val _parent: Option[Module] = Builder.currentModule
+  _parent.foreach(_.addId(this))
+
+  private[chisel3] val _id: Long = Builder.idGen.next
+  override def hashCode: Int = _id.toInt
+  override def equals(that: Any): Boolean = that match {
+    case x: HasId => _id == x._id
+    case _ => false
+  }
+
+  // Facilities for 'suggesting' a name to this.
+  // Post-name hooks called to carry the suggestion to other candidates as needed
+  private var suggested_name: Option[String] = None
+  private val postname_hooks = scala.collection.mutable.ListBuffer.empty[String=>Unit]
+  // Only takes the first suggestion!
+  def suggestName(name: =>String): this.type = {
+    if(suggested_name.isEmpty) suggested_name = Some(name)
+    for(hook <- postname_hooks) { hook(name) }
+    this
+  }
+  private[chisel3] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook
+
+  // Uses a namespace to convert suggestion into a true name
+  // Will not do any naming if the reference already assigned.
+  // (e.g. tried to suggest a name to part of a Bundle)
+  private[chisel3] def forceName(default: =>String, namespace: Namespace): Unit =
+    if(_ref.isEmpty) {
+      val candidate_name = suggested_name.getOrElse(default)
+      val available_name = namespace.name(candidate_name)
+      setRef(Ref(available_name))
+    }
+
+  private var _ref: Option[Arg] = None
+  private[chisel3] def setRef(imm: Arg): Unit = _ref = Some(imm)
+  private[chisel3] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
+  private[chisel3] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
+  private[chisel3] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
+  private[chisel3] def getRef: Arg = _ref.get
+
+  // Implementation of public methods.
+  def instanceName = _parent match {
+    case Some(p) => p._component match {
+      case Some(c) => getRef fullName c
+      case None => throwException("signalName/pathName should be called after circuit elaboration")
+    }
+    case None => throwException("this cannot happen")
+  }
+  def pathName = _parent match {
+    case None => instanceName
+    case Some(p) => s"${p.pathName}.$instanceName"
+  }
+  def parentPathName = _parent match {
+    case Some(p) => p.pathName
+    case None => throwException(s"$instanceName doesn't have a parent")
+  }
+  def parentModName = _parent match {
+    case Some(p) => p.modName
+    case None => throwException(s"$instanceName doesn't have a parent")
+  }
+}
+
+private[chisel3] class DynamicContext() {
+  val idGen = new IdGen
+  val globalNamespace = new Namespace(None, Set())
+  val components = ArrayBuffer[Component]()
+  var currentModule: Option[Module] = None
+  val errors = new ErrorLog
+}
+
+private[chisel3] object Builder {
+  // All global mutable state must be referenced via dynamicContextVar!!
+  private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None)
+  private def dynamicContext: DynamicContext =
+    dynamicContextVar.value.getOrElse(new DynamicContext)
+
+  def idGen: IdGen = dynamicContext.idGen
+  def globalNamespace: Namespace = dynamicContext.globalNamespace
+  def components: ArrayBuffer[Component] = dynamicContext.components
+
+  def currentModule: Option[Module] = dynamicContext.currentModule
+  def currentModule_=(target: Option[Module]): Unit = {
+    dynamicContext.currentModule = target
+  }
+  def forcedModule: Module = currentModule match {
+    case Some(module) => module
+    case None => throw new Exception(
+      "Error: Not in a Module. Likely cause: Missed Module() wrap or bare chisel API call."
+      // A bare api call is, e.g. calling Wire() from the scala console).
+    )
+  }
+
+  // TODO(twigg): Ideally, binding checks and new bindings would all occur here
+  // However, rest of frontend can't support this yet.
+  def pushCommand[T <: Command](c: T): T = {
+    forcedModule._commands += c
+    c
+  }
+  def pushOp[T <: Data](cmd: DefPrim[T]): T = {
+    // Bind each element of the returned Data to being a Op
+    Binding.bind(cmd.id, OpBinder(forcedModule), "Error: During op creation, fresh result")
+    pushCommand(cmd).id
+  }
+
+  def errors: ErrorLog = dynamicContext.errors
+  def error(m: => String): Unit = errors.error(m)
+  def warning(m: => String): Unit = errors.warning(m)
+  def deprecated(m: => String): Unit = errors.deprecated(m)
+
+  def build[T <: Module](f: => T): Circuit = {
+    dynamicContextVar.withValue(Some(new DynamicContext())) {
+      errors.info("Elaborating design...")
+      val mod = f
+      mod.forceName(mod.name, globalNamespace)
+      errors.checkpoint()
+      errors.info("Done elaborating.")
+
+      Circuit(components.last.name, components)
+    }
+  }
+}
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/Error.scala b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
index 6c4c0880..c5c67da4 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/Error.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
@@ -1,20 +1,20 @@
 // See LICENSE for license details.
 
-package Chisel.internal
+package chisel3.internal
 
 import scala.collection.mutable.ArrayBuffer
 
-import Chisel._
+import chisel3.core._
 
 class ChiselException(message: String, cause: Throwable) extends Exception(message, cause)
 
-private[Chisel] object throwException {
+private[chisel3] object throwException {
   def apply(s: String, t: Throwable = null): Nothing =
     throw new ChiselException(s, t)
 }
 
 /** Records and reports runtime errors and warnings. */
-private[Chisel] class ErrorLog {
+private[chisel3] class ErrorLog {
   def hasErrors: Boolean = errors.exists(_.isFatal)
 
   /** Log an error message */
@@ -25,6 +25,10 @@ private[Chisel] class ErrorLog {
   def warning(m: => String): Unit =
     errors += new Warning(m, getUserLineNumber)
 
+  /** Log a deprecation warning message */
+  def deprecated(m: => String): Unit =
+    errors += new DeprecationWarning(m, getUserLineNumber)
+
   /** Emit an informational message */
   def info(m: String): Unit =
     println(new Info("[%2.3f] %s".format(elapsedTime/1e3, m), None))  // scalastyle:ignore regex
@@ -86,6 +90,10 @@ private class Warning(msg: => String, line: Option[StackTraceElement]) extends L
   def format: String = tag("warn", Console.YELLOW)
 }
 
+private class DeprecationWarning(msg: => String, line: Option[StackTraceElement]) extends LogEntry(msg, line) {
+  def format: String = tag("warn", Console.CYAN)
+}
+
 private class Info(msg: => String, line: Option[StackTraceElement]) extends LogEntry(msg, line) {
   def format: String = tag("info", Console.MAGENTA)
 }
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/SourceInfo.scala b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
index 66bfc7a4..5e3bf33e 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/SourceInfo.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
@@ -12,7 +12,7 @@
 // writers to append source locator information at the point of a library
 // function invocation.
 
-package Chisel.internal.sourceinfo
+package chisel3.internal.sourceinfo
 
 import scala.language.experimental.macros
 import scala.reflect.macros.blackbox.Context
@@ -42,7 +42,7 @@ object SourceInfoMacro {
   def generate_source_info(c: Context): c.Tree = {
     import c.universe._
     val p = c.enclosingPosition
-    q"_root_.Chisel.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})"
+    q"_root_.chisel3.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})"
   }
 }
 
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 62784cee..0641686c 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -1,9 +1,11 @@
 // See LICENSE for license details.
 
-package Chisel.internal.firrtl
-import Chisel._
-import Chisel.internal._
-import Chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo}
+package chisel3.internal.firrtl
+
+import chisel3._
+import core._
+import chisel3.internal._
+import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo}
 
 case class PrimOp(val name: String) {
   override def toString: String = name
@@ -40,6 +42,7 @@ object PrimOp {
   val ConvertOp = PrimOp("cvt")
   val AsUIntOp = PrimOp("asUInt")
   val AsSIntOp = PrimOp("asSInt")
+  val AsClockOp = PrimOp("asClock")
 }
 
 abstract class Arg {
@@ -53,8 +56,8 @@ case class Node(id: HasId) extends Arg {
 }
 
 abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
-  private[Chisel] def forcedWidth = widthArg.known
-  private[Chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
+  private[chisel3] def forcedWidth = widthArg.known
+  private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
 
   protected def minWidth: Int
   if (forcedWidth) {
@@ -164,25 +167,9 @@ case class WhenEnd(sourceInfo: SourceInfo) extends Command
 case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
 case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
 case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
-case class Stop(sourceInfo: SourceInfo, clk: Arg, ret: Int) extends Command
+case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command
 case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg
 case class Port(id: Data, dir: Direction)
-case class Printf(sourceInfo: SourceInfo, clk: Arg, formatIn: String, ids: Seq[Arg]) extends Command {
-  require(formatIn.forall(c => c.toInt > 0 && c.toInt < 128), "format strings must comprise non-null ASCII values")
-  def format: String = {
-    def escaped(x: Char) = {
-      require(x.toInt >= 0)
-      if (x == '"' || x == '\\') {
-        s"\\${x}"
-      } else if (x == '\n') {
-        "\\n"
-      } else {
-        require(x.toInt >= 32) // TODO \xNN once FIRRTL issue #59 is resolved
-        x
-      }
-    }
-    formatIn.map(escaped _).mkString
-  }
-}
+case class Printf(sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Command
 
 case class Circuit(name: String, components: Seq[Component])