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2017-05-03Clear clock and reset scope for RawModule (#607)Richard Lin
2017-04-26Deprecate fromBits and clock/reset constructors (#583)Richard Lin
2017-04-26Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)Jim Lawson
* Remove explicit import of NotStrict - fixes #492 * Provide macro for MemBase.apply(). * Provide macro for MemBase.apply(). Since a macro cannot override an abstract method, provide a concrete apply method n VecLike() that we can override with a macro. * Remove concrete apply() in VecLike. Since MemBase no longer extends the trait VecLike, we do not require a concrete method to which we can apply a macro to extract the appropriate CompileOptions. * Add missing implicit compileOptions to do_pad() and do_zext(). The latter caused: ``` [error] /vm/home/jenkins/workspace/rocket-chip_with_chisel3/hardfloat/src/main/scala/MulAddRecFN.scala:205: too many arguments for method do_zext: (implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo)chisel3.core.SInt [error] val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext ``` * Add SourceInfoTransform macros to Vec methods in order to avoid apply() chain issues. Since utils methods are no longer NotStrict, Pipe objects need access to the client's compile options. There may be more. * Respond to review comments. Don't propagate SourceInfo through helper functions. Replace old usages of CompileOptionsTransform with the now equivalent SourceInfoTransform and redefine CompileOptionsTransform to only deal with CompileOptions. Just thread CompileOptions (not SourceInfo) through deprecated functions.
2017-04-25Remove explicit import of NotStrict - fixes #492 (#494)Jim Lawson
* Remove explicit import of NotStrict - fixes #492 * Provide macro for MemBase.apply(). * Provide macro for MemBase.apply(). Since a macro cannot override an abstract method, provide a concrete apply method n VecLike() that we can override with a macro. * Remove concrete apply() in VecLike. Since MemBase no longer extends the trait VecLike, we do not require a concrete method to which we can apply a macro to extract the appropriate CompileOptions.
2017-04-21Remove VecLike/IndexedSeq from Mem type (#589)Richard Lin
2017-04-15 Fix assignment from 0-entry Vec: add test (#580)Andrew Waterman
* Partially revert 8e4ddc62db448b613ae327792e72defca4d115d4 It was an incomplete fix for handling Vec(0). * Fix assignment from 0-entry Vec: add test 375e2b6a0a456c55298d82837d28986de6211ebc introduced a regression for bundles containing zero-entry Vecs. Until zero-width UInts are supported, the zero-entry Vecs need to be flattened out before doing asUInt/asTypeOf on a bundle. Undoing that commit's replacement of Data.flatten with Aggregate.getElements is the best interim fix.
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-04-12Fix one hot mux (#573)Chick Markley
* still trying to find right mix * Making some progress on Mux1H * Mux1H that works in non-optimzed fashion for FixedPoint, works pretty well in general Catches some additional problem edge cases Some tests that illustrate most of this * Moved in Angie's code for handling FixedPoint case Cleaned up tests considerably, per @ducky64 review * Just a bit more cleanup
2017-04-04Use input element to decide if Vec of values has direction (#570)Jack Koenig
Using the sample_element of the created wire is incorrect because Wires have no direction so the Wire constructed for a Vec of Module IO was constructed incorrectly. Fixes #569 and resolves #522.
2017-04-04Define CompileOptions case class to support CompileOptions manipulation. (#572)Jim Lawson
Make it relatively easy to override a single CompileOption.
2017-04-02Make Module instantiations draw clock from Builder instead of parent (#568)Jack Koenig
Fixes #567
2017-03-28Creating FixedPoint literals was throwing away width when specifically provided.chick
This caused one hot muxing problems in dsptools FixedPoint spec fixed based on error uncovered by this change
2017-03-27Support Vec(0) fields in Bundles, just like Option[Data]; add testAndrew Waterman
This also allows asUInt/asTypeOf to work properly on those Bundles, even though zero-width wire support is lacking.
2017-03-24Fix getWidth on empty Vecs; add testAndrew Waterman
Use fold(0) instead of reduce to handle the corner case.
2017-03-24Fixed fix, allow Mux of different binary points and widths (#559)Richard Lin
Allow muxing FxP of different widths and BPs
2017-03-13Revert "Change Vec creation to check if gen is lit (and hence needs t… (#530)Jim Lawson
* Revert "Change Vec creation to check if gen is lit (and hence needs to be declared)" This reverts commit dc86e7e1734d6abacb739b488df1de231e6b41b2. This may address #522 - using chiselCloneType (instead of cloneType) to preserve directionality. * Add missing implicits to Vec.apply() signature. * Use correct macro (CompileOptionsTransform) for indexWhere.
2017-03-08Deprecate old Reg with nulls constructor (#455)Richard Lin
2017-02-27Record: allow elements to start with a digitWesley W. Terpstra
This is necessary for user-defined Record-derived types to retain the same signal name as they would using a Vec.
2017-02-24Fix mismatch between Chisel and Firrtl on UInt -& UIntJack Koenig
Fixes #501. Also added UIntOps test.
2017-02-24Escape % in assertion messagesJack Koenig
2017-02-23Fend off future bug - replace FixedPoint ":=" with "connect". (#516)Jim Lawson
This turned up after updating #494 (Remove explicit import of NotStrict) and adding the missing implicit CompileOptions to ":="'s signature at which point Scala pointed out FixedPoint's ":=" could not override Data's final ":=" with the same signature: the implicit time bomb.
2017-02-22Bugfix #513. Fix BPSet width inference in Chisel3 (#523)Adam Izraelevitz
* Bugfix #513. Needs better test case * Improved test
2017-02-17Builderreflectionfix (#515)Angie Wang
* change builder for bundle reflection fix * fixed bug -- should be not assignable
2017-02-16Add scaladoc examples for Vec and Bundle (#511)Chick Markley
* Add scaladoc examples for Vec and Bundle * address comments, added @example tag eliminate extraneous context * address comments, added @example tag eliminate extraneous context * ok, I've wrestled with the javadoc sytnax, the following commit, is my best result so far
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
withClockAndReset, withReset, and withClock allow changing the implicit clock and reset. Module.clock and Module.reset provide access to the current implicit clock and reset.
2017-02-15Blackbox comments spelling correction thanks to edwardcwangFabien Marteau
2017-02-15BlackBox documentation: adding the verilog template to generateFabien Marteau
2017-02-15Adding a BlackBox example in code documentationFabien Marteau
2017-02-15Implement asTypeOf, refactor internal APIs (#450)Richard Lin
2017-02-15Fixed point factory stuff (#505)Chick Markley
* Don't allow analog to analog monoconnect adjust tests accordingly * demonstrate bit loss in shift right for fixed point * cleaned up some stuff. this does not test clean due to bug in firrtl
2017-02-08Add Analog typeJack Koenig
Used for stitching Verilog inout through Chisel Modules (from BlackBox to BlackBox)
2017-02-08Add counter for depth of when scopeJack Koenig
2017-02-07Fix up Absolute value #abs (#491)Chick Markley
* Fix up Absolute value #abs Defines #abs in Num Implement #abs in UInt Change #abs in SInt to return an SInt Change #abs in FixedPoint to return a FixedPoint Added a couple of tests Add some scala style suppression to Bits so I can read code in IntelliJ * Per review Add tests that abs works for positive values Added SInt and UInt tests for abs to new underpopulated IntegerMathSpec Used fixed point literals in fixed points abs definition
2017-02-07Add macro for compile options materialize to prevent its use in chisel coreducky
2017-02-07Rename SeqMem to SyncReadMem. (#490)Jim Lawson
Retain un-deprecated SeqMem in compatibility mode, deprecate in chisel3.
2017-02-03Added vec IO tests for #104 (#480)Jim Lawson
* Added vec IO tests for #104 * Added Vec test case for Reg of vecs * Change Vec creation to check if gen is lit (and hence needs to be declared) Fixes #104 * Fix tests (add IO())), Vec.fill() * Fix deprecated usage. * Add Binding IO() NPE fix so tests pass. * Fix style - use space consistently. * Fix style - use space consistently.
2017-02-03Fix potential NPE if we try to evaluate isMissingIOWrapper() inside IO(). (#479)Jim Lawson
2017-01-31Make Module and Bundle properly use empty namespacesJack
Fix default suggested name of Module instances (now based on desired name rather than actual assigned name). Remove parent/child relationship from Namespace. Previously, Module and Bundle namespaces were "children" of the Module definition namespace. This could lead to collisions that would give unexpected names for module instances or Bundle elements. In particular, otherwise identical modules that instantiate other identical modules in such a way that the instance cannot be named via reflection would not be deduplicated because the names of the instances would collide with the names of the modules in the Builder.globalNamespace.
2017-01-27Clean names of private vals in Modulesjackkoenig
2017-01-27Have checkpoint report (and clear) non-fatal errors. (#376)Jim Lawson
2017-01-25Better name propagation by macros (#327)Richard Lin
* Name propagation * chiselName everywhere at best-effort level * Better collision handling * Allow recursing into inner anonymous functions * Add for loop and anonymous inner function tests
2017-01-20Add Record as new superclass of Bundle (#366)Jack Koenig
Record gives uses the power to create collections of heterogenous elements. Bundle is a special case of Record that uses reflection to populate the elements of the collection. Bundle also attempts to implement cloneType whereas users of Record are required to supply one.
2017-01-13Make fromBits work with types other than UInt (#424)grebe
* Make fromBits work with types other than UInt * Oops, left in a println * Add test for truncation/expansion * Fix stuff that broke when FixedPoint fromBits PR was merged. * Use .BP shorthand added in previous PR
2016-12-22Merge branch 'master' into fixedPointFromBitsgrebe
2016-12-19Merge branch 'master' into exceptionfixJim Lawson
2016-12-13Fix test.Paul Rigge
2016-12-13CheckpointPaul Rigge
2016-12-13Have FixedPoint use asFixedPoint in fromBits.Paul Rigge
2016-12-07Support for creating chisel annotations that are consumed by firrtl (#393)Chick Markley
* Support for creating chisel annotations that are consumed by firrtl Update annotation serialization in Driver Add DiamondAnnotation Spec that illustrates how to do simple annotations frontEnd must have dependency on firrtl Add annotation method to Module Circuit has extra optional parameter that is Seq of Annotations In Builder add annotation buffer to DynamicContext to store annotations created in modules Added explicit types on naming api methods to avoid type confusion Because some names are not available until elaboration create intermediate ChiselAnnotation that gets turned into a firrtl Annotation after elaboration In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though intermediate file .fir and .anno files are still created for inspection and/or later use * Somehow missed ChiselAnnotation * fixes for Jack's review of PR
2016-12-05Merge branch 'master' into exceptionfixJack Koenig
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