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path: root/chiselFrontend/src/main/scala/chisel3
AgeCommit message (Expand)Author
2016-09-21Expose FIRRTL asClock constructAndrew Waterman
2016-09-21Make implicit clock name consistent (#288)Andrew Waterman
2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
2016-09-07Add Printable (#270)Jack Koenig
2016-09-02Deprecate asBits; modify deprecation warnings accordinglyAndrew Waterman
2016-09-01Remove O(n^2) code in Vec.apply(Seq)Andrew Waterman
2016-08-31Check that Vecs have homogeneous typesAndrew Waterman
2016-08-24Per Chisel meeting.chick
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
2016-08-16Add component to signature.Jim Lawson
2016-08-16Provide public SignalID trait to be used to conjure up a signal identifier.Jim Lawson
2016-08-15Make "def width" a private API; expose isWidthKnown instead (#257)Andrew Waterman
2016-08-09Support Module name overrides with "override def desiredName"Andrew Waterman
2016-08-09Legalize identifier names before printingAndrew Waterman
2016-07-31Expose asUInt from DataAndrew Waterman
2016-07-31Fix two deprecation warningsAndrew Waterman
2016-07-20Generate better names for nodes (#190)Jack Koenig
2016-07-15Improve PopCount implementationAndrew Waterman
2016-07-01Reflectively name Module fields declared in superclassesAndrew Waterman
2016-06-24Merge branch 'master' into renamechisel3Jim Lawson
2016-06-22Merge branch 'master' into renamechisel3Jim Lawson
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson
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