chiselX - Chisel with SFC compatibility

Age	Commit message (Collapse)	Author
2017-02-08	Add Analog type	Jack Koenig
	Used for stitching Verilog inout through Chisel Modules (from BlackBox to BlackBox)
2016-12-07	Support for creating chisel annotations that are consumed by firrtl (#393)	Chick Markley
	* Support for creating chisel annotations that are consumed by firrtl Update annotation serialization in Driver Add DiamondAnnotation Spec that illustrates how to do simple annotations frontEnd must have dependency on firrtl Add annotation method to Module Circuit has extra optional parameter that is Seq of Annotations In Builder add annotation buffer to DynamicContext to store annotations created in modules Added explicit types on naming api methods to avoid type confusion Because some names are not available until elaboration create intermediate ChiselAnnotation that gets turned into a firrtl Annotation after elaboration In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though intermediate file .fir and .anno files are still created for inspection and/or later use * Somehow missed ChiselAnnotation * fixes for Jack's review of PR
2016-12-01	Fix spelling of "specified". (#392)	Jim Lawson

2016-11-21	Fix open-open range specifier, remove dead code, restyle tests	ducky

2016-11-21	first attack on creating a range api for chisel3	chick

2016-11-18	Add support for parameterized BlackBoxes	jackkoenig
	Also restrict black boxes to not allow hardware inside of them since it was being silently dropped anyway. Resolves #289
2016-10-25	FixedPoint number support for chisel3 (#328)	Chick Markley
	* FixedPoint number support for chisel3 FixedPoint numbers have a width and a binary position Either, neither or both maybe inferred. Firrtl will convert these to SInts during lowering passes * Fixes based on Jack's comments on PR #328 * Add experimental warning to FixedPoint class and object * Fixed comment per Adam's comment on PR #328
2016-09-21	Expose FIRRTL asClock construct	Andrew Waterman
	Additionally, fix Clock.asUInt (previously, it threw an esoteric exception), and add a simple test of both.
2016-09-21	Make implicit clock name consistent (#288)	Andrew Waterman
	In the Chisel frontend, the implicit clock is named clock, but in the generated FIRRTL, it is named clk. There is no reason for this discrepancy, and yet fixing it is painful, as it will break test harnesses. Better to take the pain now than later. Resolves #258.
2016-09-07	Add Printable (#270)	Jack Koenig
	Printable is a new type that changes how printing of Chisel types is represented It uses an ordered collection rather than a format string and specifiers Features: - Custom String Interpolator for Scala-like printf - String-like manipulation of "hardware strings" for custom pretty-printing - Default pretty-printing for Chisel data types
2016-06-20	Rename "package", "import", and explicit references to "chisel3".	Jim Lawson

2016-06-20	Rename chisel3 package.	Jim Lawson