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* Rename coreMacros to macros
* Rename chiselFrontend to core
Also make each subproject publish with "chisel3-" as a prefix
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Change the emission strategy for Bits methods andR and orR to emit
FIRRTL bitwise reduce operations andr and orr.
Add two tests that assert the correct behavior of these operations in
BitwiseOpsSpec.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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'108'. (#1309)
Co-authored-by: Chick Markley <chick@qrhino.com>
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decimal
- made .F and .I work for creating fixed point and interval lits from big decimal
- Added NumObject trait which provides new math conversions
- Made a Num object that extends NumObject
- Add this trait to FixedPoint and Interval for backward compatibility
- Removed code that is now in NumObject, keeping things DRY
- Add tests to FixedPointSpec to show lit conversion to double and big decimal
- Add tests to IntervalSpec to show lit conversion to double and big decimal
- Add tests to LiteralExtractorSpec to show general math conversions between BigInts with binary points and double and big decimal
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Plan to be released with 3.3.
Breaks experimental Range API.
Adds new Interval type and associated support.
This commit adds the following:
- Renamed Range to IntervalRange to avoid name collision with scala Range
- Changed RangeTransform macro to Return an IntervalRange
- Improved error messages on missing comma or decimal
- Added notational support for binary point
- Some formatting cleanup also
- SIntFactory
- Change to use IntervalRange API
- UIntFactory
- UInt from range has custom width computation
- It does not need to deal with lowerbound extending bit requirements
- Code to handle special case of range"[0,0]" to have a width of 1
- IR.scala
- Removed Bound and other constraint code that was duplicating firrtl stuff
- Added new RangeType
- Added IntervalRange class and object
- RangeSpec
- modified just a bit to handle notational differences
- previous range interpolator returned tuple now returns IntervalRange
- Add IntervalType to emitter
- Added IntervalSpec with many tests
- Added ScalaIntervalSimulatorSpec which tests golden model for Interval
- Added ScalaIntervalSimulator which is a golden model for Interval
- This gold may not have been polished to a high sheen
- Add IntervalLit cases to Converter
- Add Interval PrimOps to IR
- asInterval, wrap, squz, clip, setp, decp, incp
- Add IntervalLit class to IR
- Add Interval to MonoConnect
- Add Interval Type to Bits (in experimental package)
- add conversions to Interval from other types
- Add Interval clone stuff to Data
- Add Literal creation helpers to chisel3 package
- these may move to experimental if I can figure that out
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changes)
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Adds new AsyncReset and "abstract" Reset types. Reset is inferred
in FIRRTL to be either AsyncReset or Bool. The "reset type" of a
register is set by the type of its reset signal:
val asyncReset: AsyncReset = IO(Input(AsyncReset()))
val syncReset: Bool = IO(Input(Bool()))
val abstractReset: Reset = IO(Input(Reset()))
val asyncReg = withReset(asyncReset) { RegInit(0.U) }
val syncReg = withReset(syncReset) { RegInit(0.U) }
val inferredReg = withReset(abstractReset) { RegInit(0.U) }
AsyncReset can be cast to and from Bool. Whereas synchronous reset is
equivalent to a mux in front of a flip-flop and thus can be driven by
logic, asynchronous reset requires that the reset value is a constant.
This is checked in FIRRTL.
Inference of the concrete type of a Reset occurs based on the type the
Reset's drivers. This inference is very simple, it is simple forward propagation
of the type, but it allows for writing blocks and modules that are agnostic
to the reset type. In particular, the implicit `reset` value in MultiIOModule
and thus Module is now concretely an instance of Reset and thus will be
inferred in FIRRTL.
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This renames all *FactoryBase traits to *Factory, removes
transparent *Factory objects, and propagates this flattened hierarchy
throughout the codebase.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Anything removed by this that is used by the compatibility layer is
migrated to the compatibility layer.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Change Num.+ Scaladoc to state that this is not a growing
addition. Note that this is problematic either way as this macro is
resolved to an abstract method. Classes implementing this typeclass
are technically free to violate what we put in the Scaladoc here.
h/t @kammoh
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
* Move Aggregate, Clock, Mem, Printf, Reg
* Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
* Revive core package object to provide aliases for moved definitions.
* Cleanup package definitions; eliminate ambiguous implicits
* Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
* Put BitPat back in chisel3.util
* More experimental motion - avoid multiple import definitions.
* Add experimental.FixedPoint alias
* Add EnumType definition to core package.
Update deprecated messages to refer to correct object
* Move FixedPoint into the experimental package (but keep it in Bits.scala).
* Add missing implicits to core/package - compatibility
* Cleanup: update ScalaDoc references; remove unused imports
* Add Reset alias to core/package
* Use common 3.2 version in deprecation warning
* Move Binding from core to internal.
* Optimize imports.
* Repair IntelliJ's overly cleanliness.
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
* Change == to reference equality (eq) in Data print (#1044)
* Remove @chiselName from MixedVec (#1045)
* Fix enum annotations (#936)
* Turned off strong enum annotations because they weren't working with Vec
indexes
* Add new EnumVecAnnotation for vecs of enums and vecs of bundles with
enum fields
* Changed Clock's width parameter back to a fixed constant value of 1
* Fixed enum annotations for Vecs of Bundles which contain enum elements
* Fixed usage of "when/otherwise" to use consistent style
* Add Record to type hierarchy documentation
* Undeprecate isLit (#1048)
* move doNotDedup to experimental (#1008)
* Aggregate coverage - aggregate tests but not publishing (#1040)
Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
This should finally fix #772.
* Check field referential equality in autoclonetype (#1047)
* Allow naming annotation to work outside builder context (#1051)
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Make core.DontCare private to chisel3 (#1054)
Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Detect bundle aliasing (#1050)
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Optimize imports.
* Move Analog to experimental.
* More repackage cleanup - reduce differences with master.
* Cleanup chisel3 references.
* More chisel3 reference cleanup.
* Merge cleanup.
* Remove unused import
* Bump core deprecation to 3.3
* Move DontCare back into Data.scala inside package internal
* Re-indent experimental/internal package code
* Move code back to original files - facilitate comparison with other branches
* Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
* More master diff minimization.
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Move Analog to experimental.
More repackage cleanup - reduce differences with master.
Cleanup chisel3 references.
More chisel3 reference cleanup.
* Fix wrong directionality for Vec(Flipped())
Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.
Close #1063
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Put BitPat back in chisel3.util
More experimental motion - avoid multiple import definitions.
Add experimental.FixedPoint alias
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Add Reset alias to core/package
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Repair IntelliJ's overly cleanliness.
Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Merge cleanup.
Remove unused import
Bump core deprecation to 3.3
Move DontCare back into Data.scala inside package internal
Re-indent experimental/internal package code
Move code back to original files - facilitate comparison with other branches
Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
More master diff minimization.
Fix minor discrepancies with repackagecore-testbed
* Remove redundant imports
As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._`
* Move the BaseModule object into the internal package.
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