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2019-02-19Update README to reference the bootcamp (#1025)Paul Rigge
* Update README to reference the bootcamp * Place learning section higher
2019-02-19Merge pull request #1017 from freechipsproject/scaladoc-TransitNameSchuyler Eldridge
- Add Scaladoc for chisel3.util.TransitName - Add test for TransitName
2019-02-19Add TransitNameSpecSchuyler Eldridge
This adds a test of chisel3.util.TransitName (which is used for the TransitName documentation). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Add Scaladoc for chisel3.util.TransitNameSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Mainline Chisel multi-clock functionality (#1013)edwardcwang
Close #1009
2019-02-19Util doc lsfr (#1021)Chick Markley
* Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Fixed typos in LFSR - Reduce trials a little - Add test of LFSR period * Update documentation for LSFR16 - Fixed remaining LSFR, arrgh - Removed intellij specific warning suppressor - Fixed comments/scaladoc wording and case. * Update documentation for LSFR16 - Use printable interpolator as example of printing out a Vec
2019-02-19Documentation for Reg utilities (#1018)Martin Schoeberl
2019-02-19ScalaDoc for OneHot (#1016)Martin Schoeberl
2019-02-19Merge pull request #1023 from freechipsproject/scaladoc-ValidSchuyler Eldridge
Valid/Pipe Improvements: Scaladoc, latency requirement
2019-02-18Add requirement that Pipe latency >= 0Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-18Add Scaladoc for chisel3.util.PipeSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-18Add Scaldoc for chisel3.util.ValidSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-01Queue TestsBrendan Sweeney
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-23Use Verilator 4.006; bump to Scala 2.12.7 (#947)Jim Lawson
Now that ucbbar/chisel3-tools has Verilator 4.006, use that for tests.
2019-01-23Bump copyright year (#997)Jim Lawson
2019-01-22Import aliases for chisel3.core (#998)Richard Lin
Compatibility for rename introduced by #994
2019-01-22Define Data .toString (#985)Richard Lin
toString on Data subtypes will now print the type and optionally binding information including literals and IO names as feasible.
2019-01-22Remove ghpages (#992)Jim Lawson
* Remove GhpagesPlugin. (#966) * Restore old SCM reference (after removing ghpages)
2019-01-22Merge pull request #978 from seldridge/boring-utils-dedup-fixSchuyler Eldridge
- Fix BoringUtils deduplication bug, include new tests - Update/clarify BoringUtils scaladoc
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
This compresses the Scaladoc for BoringUtils slightly by using 120 character lines and removing unnecessary whitespace. This also changes the poorly named "dedup" parameter to the what it actually is: "disableDedup". Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Fix BoringUtilsSpec to require no dedupSchuyler Eldridge
This adds two tests to the BoringUtilsSpec to explicitly verify that deduplication is required when boring. This adds tests that both verify that the test passes as expected with deduplication enabled and that the same test fails with deduplication disabled. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Fix BoringUtils deduplication bugSchuyler Eldridge
This fixes a bug where BoringUtils non-hierarchical sinks would be deduplicated even when specified that they should not be. h/t @ucbjrl for discovering this! Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943)Albert Magyar
2019-01-21Support DontCare in Mux and cloneSupertype (#995)Richard Lin
2019-01-21Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) ↵Richard Lin
Module class names (#994)
2019-01-18Remove bin (#991)Richard Lin
2019-01-17Merge pull request #987 from freechipsproject/unary-not-fixSchuyler Eldridge
Fix scaladoc for UInt.unary_!
2019-01-17Unary_- is truncatingAndrew Waterman
2019-01-17Make combinational-multiplier warning less vagueAndrew Waterman
2019-01-17Improve description of UInt.asSIntAndrew Waterman
2019-01-17Fix width-inference description of Bits.<<Andrew Waterman
2019-01-17Fix scaladoc for UInt.unary_!Andrew Waterman
It performs the operation (x === 0.U), just like in C. The scaladoc incorrectly described it as performing the operation !x(0). (Obviously, these are equivalent for Bool, but not for UInt in general).
2019-01-17Merge pull request #988 from freechipsproject/improve-andrSchuyler Eldridge
Generate better code for UInt.andR
2019-01-17Merge branch 'master' into improve-andrSchuyler Eldridge
2019-01-17Generate better code for UInt.andRAndrew Waterman
In the case that the width is known, we can emit one fewer Firrtl node. This obviously synthesizes the same way, but compiles/simulates faster.
2019-01-11Add test for chiselNaming of Seq[Data]Andrew Waterman
2019-01-11For chiselName, use nameRecursively rather than matching on HasIdAndrew Waterman
2019-01-11Move nameRecursively into Builder so it can be used elsewhereAndrew Waterman
2019-01-09Merge pull request #979 from seldridge/procedural-wire-assignmentSchuyler Eldridge
Avoid procedural wire assignment in test resource
2019-01-09Avoid procedural wire assignment in test resourceSchuyler Eldridge
Verilator 4.008 dropped the hammer on procedural wire assignment to align with the IEEE standard (first I've heard of this, though). The VerilogVendingMachine.v test resource will error in Verilator 4.008 with a PROCASSWIRE error if you try to compile it. This fixes that example to only assign to a register. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-07Fix build error due to scala bug #11125 (#967)Nick Hynes
JDK 11 `java.lang.String#lines` conflicts with Scala `StringOps#lines`. This has been fixed in scalac 2.12.8 but projects using 2.11 in their cross-build need the `Predef.augmentString` patch. [Scala bug & fix reference](https://github.com/scala/bug/issues/11125)
2019-01-07Add explicit Sonatype resolvers so SNAPSHOTs can be found remotely. (#975)Jim Lawson
**NOTE**: A `publishLocal` should replace the downloaded `.ivy2/cache/...` version with a pointer to the `.ivy2/local/...` version. To force refetching of the Sonatype repository version, you should delete both `.ivy2/{cache,local}/...` versions.
2018-12-23Add Windows setup instructions to readme (#964)Richard Lin
2018-12-19Fix width inferencing issue (#952)Jack Koenig
* Fix width propagation of non-literals in WireInit and RegInit * Change .getWidth to throw an exception instead of calling .get * Add utilities for checking inferred vs. known widths * Add tests for Wire, WireInit, Reg, and RegInit width inference * Add ScalaDoc for Reg, Wire, RegInit, and WireInit
2018-12-11Merge pull request #961 from freechipsproject/subwrapSchuyler Eldridge
Improve quality of code generation for UInt.-%
2018-12-11Emit UInt.-% as tail(sub(x,y),1), not tail(asUInt(sub(x,y)),1)Andrew Waterman
This is semantically equivalent, but gets rid of a bunch of Firrtl text. It also gets rid of a bunch of Verilog, because Firrtl is capable of pattern-matching the new expression into SubWrap. The effect is that we now get wire [4:0] in; wire [4:0] res; assign res = 5'h0 - in; instead of wire [4:0] in; wire [5:0] _T_40; wire [5:0] _T_41; wire [4:0] res; assign _T_40 = 5'h0 - in; assign _T_41 = $unsigned(_T_40); assign res = _T_41[4:0];
2018-12-06Bump SBT from 1.2.6 to 1.2.7 to fix partial recompilation issue (#956)Jack Koenig
2018-12-04Merge pull request #950 from freechipsproject/as-boolsJack Koenig
asBools, asBool, and chained apply on asBools
2018-12-04Add asBool, deprecate toBoolJack Koenig
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