diff options
| author | Schuyler Eldridge | 2019-02-18 20:06:58 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-02-18 20:06:58 -0500 |
| commit | 32828f3fd64e75a937d67634d60e6e914417ef09 (patch) | |
| tree | 7be7296c258e325552e1977a3b404144c4517c11 | |
| parent | 658e7f6af7b40842f2777c5cc6968e599bd32334 (diff) | |
Add requirement that Pipe latency >= 0
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index df458927..7dcad2c7 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -111,6 +111,7 @@ object Pipe { */ @chiselName def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T] = { + require(latency >= 0, "Pipe latency must be greater than or equal to zero!") if (latency == 0) { val out = Wire(Valid(chiselTypeOf(enqBits))) out.valid := enqValid |