diff options
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index df458927..7dcad2c7 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -111,6 +111,7 @@ object Pipe { */ @chiselName def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T] = { + require(latency >= 0, "Pipe latency must be greater than or equal to zero!") if (latency == 0) { val out = Wire(Valid(chiselTypeOf(enqBits))) out.valid := enqValid |