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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Add a tree reduce function to Vec
* Change function names of reduce operation function in Vec
* Change reference to single layer operation in Vec.reduce
* Commint name change for pair macro
* Remove pair, call not necessary and can just be used from grouped(2) and map
* Changed to reduceTree, added default identity function for single reduce.
* Change style of Vec.reduceTree and tests to chisel3 and canonical Scala style
* Cleanup Vec initialization, implicitCompileOptions
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FIRRTL barfs on negative and zero-sized memories
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* Move dontTouch out of experimental package.
* Move RawModule, MultiIOModule out of experimental.
* Respond to comments - Move LagacyModule from experimental to internal.
*NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions.
* Fix up a few more imports.
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Switch to new API links
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Add Chisel Cheatsheet Latest Release Link
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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changes)
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Fix Stack Trace Trimming in Driver
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Use FIRRTL stage-style testing to check stdout printing without and
with --full-stacktrace.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds methods for examining stdout/stderr and exit codes inside of
a Scala program. This are pulled directly from firrtlTests, but we
aren't currently publishing those anywhere that we can get at them.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Refactor: remove redundant code
* Change to protected API
* Remove type hierarchy
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Dependency API (take 2)
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Migrate Driver to use a PhaseManager to internally resolve Phase
ordering. This requires the use of an identity node to adequately
describe the necessary prerequisite/dependents.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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Modifies ChiselStage to use a PhaseManager for Phase ordering.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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Adds new AsyncReset and "abstract" Reset types. Reset is inferred
in FIRRTL to be either AsyncReset or Bool. The "reset type" of a
register is set by the type of its reset signal:
val asyncReset: AsyncReset = IO(Input(AsyncReset()))
val syncReset: Bool = IO(Input(Bool()))
val abstractReset: Reset = IO(Input(Reset()))
val asyncReg = withReset(asyncReset) { RegInit(0.U) }
val syncReg = withReset(syncReset) { RegInit(0.U) }
val inferredReg = withReset(abstractReset) { RegInit(0.U) }
AsyncReset can be cast to and from Bool. Whereas synchronous reset is
equivalent to a mux in front of a flip-flop and thus can be driven by
logic, asynchronous reset requires that the reset value is a constant.
This is checked in FIRRTL.
Inference of the concrete type of a Reset occurs based on the type the
Reset's drivers. This inference is very simple, it is simple forward propagation
of the type, but it allows for writing blocks and modules that are agnostic
to the reset type. In particular, the implicit `reset` value in MultiIOModule
and thus Module is now concretely an instance of Reset and thus will be
inferred in FIRRTL.
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Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.
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Remove "-Xcheckinit" from build.sc
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Require target is hardware for Vec.apply(a: UInt)
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Adds a check that a Vec being indexed by a UInt is, in fact, a
hardware type. This includes a test for this.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Update website references to the new website
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Avoid when(reset) construct in LFSR
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Muxes and resets are only isomorphic with synchronous reset. Use a reset
instead of a conditional to make this async-reset-safe.
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Remove Deprecations since before 3.2
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This renames all *FactoryBase traits to *Factory, removes
transparent *Factory objects, and propagates this flattened hierarchy
throughout the codebase.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Anything removed by this that is used by the compatibility layer is
migrated to the compatibility layer.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds a clarification to the deprecation message for RawModule,
MultiIOModule, UserModule, and ImplicitModule. While these were
technically deprecated "since the beginning of time", this adds a
comment that these aliases will be removed in 3.3.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Change "since" specification from "chisel3.2" to "3.2". This aligns
with usages in the rest of the codebase.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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freechipsproject/improve-compatibility-mode-testing
Improve compatibility mode testing
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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