Merge pull request #1148 from freechipsproject/vec-vec-chisel-type-message

Require target is hardware for Vec.apply(a: UInt)

2 files changed, 12 insertions, 0 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
index 9149447a..dfba1caf 100644
--- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
@@ -216,6 +216,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int)
 
   /** @group SourceInfoTransformMacro */
   def do_apply(p: UInt)(implicit compileOptions: CompileOptions): T = {
+    requireIsHardware(this, "vec")
     requireIsHardware(p, "vec index")
     val port = gen
 
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 0884ad37..2f67f375 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -272,4 +272,15 @@ class VecSpec extends ChiselPropSpec {
       io.out := VecInit(Seq(4.U, 5.U, DontCare, 2.U))
     })
   }
+
+  property("Indexing a Chisel type Vec by a hardware type should give a sane error message") {
+    assertThrows[ExpectedHardwareException] {
+      elaborate{
+        new Module {
+          val io = IO(new Bundle{})
+          val foo = Vec(2, Bool())
+          foo(0.U) := false.B
+        }}
+    }
+  }
 }