From 9e99adbe920f3127e02a8dac05c972e3ea518c12 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 7 Aug 2019 18:00:29 -0400 Subject: Require target is hardware for Vec.apply(a: UInt) Adds a check that a Vec being indexed by a UInt is, in fact, a hardware type. This includes a test for this. Signed-off-by: Schuyler Eldridge --- chiselFrontend/src/main/scala/chisel3/Aggregate.scala | 1 + src/test/scala/chiselTests/Vec.scala | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala index 9149447a..dfba1caf 100644 --- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala @@ -216,6 +216,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) /** @group SourceInfoTransformMacro */ def do_apply(p: UInt)(implicit compileOptions: CompileOptions): T = { + requireIsHardware(this, "vec") requireIsHardware(p, "vec index") val port = gen diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 0884ad37..2f67f375 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -272,4 +272,15 @@ class VecSpec extends ChiselPropSpec { io.out := VecInit(Seq(4.U, 5.U, DontCare, 2.U)) }) } + + property("Indexing a Chisel type Vec by a hardware type should give a sane error message") { + assertThrows[ExpectedHardwareException] { + elaborate{ + new Module { + val io = IO(new Bundle{}) + val foo = Vec(2, Bool()) + foo(0.U) := false.B + }} + } + } } -- cgit v1.2.3