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2019-12-18BitPat supports whitespace and underscores, presumably for human readability.chick
The BitPat.parse factory though did not remove these from the returned count. This fixes that adds whitespace and underscores to the unit tests This is an updated vesion of Chisel PR #1069
2019-12-17Merge branch 'master' into interval-fix-2Chick Markley
2019-12-17Band aid until litOption is implemented for Aggregates. (#1277)Jim Lawson
This is just a band aid until an Aggregate `isLit()` method (for which work has begun) is implemented.
2019-12-16Remove unused WriteEmitted phase (#1273)Schuyler Eldridge
This removes a dead line where a WriteEmitted phase is constructed. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-12-12Fixed problem creating Interval literals with full rangeschick
- boundary testing was not taking binary point into account correctly - add tests to show where things work and where they are supposed to fail
2019-12-11Merge pull request #1274 from freechipsproject/interval-fix-1Chick Markley
Bug fixes to support code for Interval
2019-12-11- add simple test of IntervalRange helperschick
- getLowestPossibleValue - getHighestPossibleValue - getPossibleValues
2019-12-11- Change getPossibleValues of Interval to return a NumericRange former Seq ↵chick
materialized all values - Fixed computation in getHighestPossibleValue, erroneously was using lower intead of upper
2019-12-06Revert "Compat compile options macro (#1253)" (#1268)Jack Koenig
This reverts commit 85fe90d5b7ed4e1101b0b3959a1d362eb93915ac.
2019-12-04Add ChiselEnum to BundleLiterals (#1215)Zhuanhao Wu
2019-12-02Remove Jenkins CI from .mergify.yml (#1264)Jack Koenig
2019-12-02Fix asTypeOf for Clock (#1258)Jack Koenig
2019-11-29Merge pull request #1260 from freechipsproject/ccc20-extensionSchuyler Eldridge
Update README to reflect CCC20 Extension
2019-11-29Update README to reflect CCC20 ExtensionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-11-29Fix deprecation warning that leaks into user code (#1256)Jack Koenig
Data.isLit called Data.litArg which would trigger a Chisel runtime deprecation warning in user code with source locator Data.scala:488
2019-11-29Compat compile options macro (#1253)Jack Koenig
* Use macro to materialize CompileOptions in Chisel._ This switches from using an implicit val that required awkward suppression (as illustrated in CompileOptionsSpec) to allowing overriding in the same way as done in "import chisel3._" via the creation of an implicit val in lexical scope. * Deprecate Chisel.defaultCompileOptions
2019-11-27Fix bidirectional Wire with Analog (#1252)Jack Koenig
2019-11-22Add binary comp. check to mergify bpAdam Izraelevitz
2019-11-22Fix mergify to backports: omit jenkins CI (#1246)Adam Izraelevitz
2019-11-22Create .mergify.yml (#1244)Adam Izraelevitz
2019-11-21Add CCC20 Info at README top (#1243)Schuyler Eldridge
* Add CCC20 Info at README top Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add Upcoming Events h2 Heading to README.md Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-11-17Improve error message when assigning from Seq to Vec (#1239)Andrew Waterman
2019-11-15Enable @chiselName on non-module classes (#1209)John's Brew
2019-11-12Add brief description of (current) chisel versioning and version ↵Jim Lawson
recommendations. (#1180) * Add brief description of (current) chisel versioning and version recommendations. * Respond to comments. Replace "semantic versioning" with "a form of semantic versioning". * Respond to comments - replace mmddyy with yyyymmdd. * Mention change in SNAPSHOT naming.
2019-11-06Merge pull request #1201 from freechipsproject/full-MuxLookupSchuyler Eldridge
Don't use MuxLookup default for full mapping
2019-11-05Add tests for exhaustive MuxLookup optimizationAlbert Magyar
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2019-11-05Don't use MuxLookup default for full mappingSchuyler Eldridge
This modifies MuxLookup to not use the 'default' mapping argument if a "full" mapping is provided. A "full" mapping enumerates all possible cases for a 'key' argument of a known size. This will check literal values to ensure exhaustiveness holds. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2019-11-05Support literals cast to aggregates as async reset reg init values (#1225)Jack Koenig
Accomplished by changing the code gen for casting literals to aggregates. Rather than connecting the literal to a wire that is then bit selected from, just bit select from the literal which saves the creation of an intermediate wire and matches FIRRTL's semantics for legal async reset initial values.
2019-11-05Bump master SNAPSHOT version. (#1227)Jim Lawson
2019-11-02Merge pull request #1224 from freechipsproject/issue-1223Schuyler Eldridge
Improve naming of anonymous/class-in-function Modules
2019-11-02Tests for anonymous/class-in-module desiredNameSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-11-02Better anonymous and class-in-function desiredNameSchuyler Eldridge
This changes the desired name of a Module to provide non-numeric naming for anonymous Modules and Modules defined inside function bodies. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-23Merge pull request #1216 from freechipsproject/non-private-ChiselStage-targetsSchuyler Eldridge
Make ChiselStage targets not private
2019-10-23Make ChiselStage targets not privateColin Schmidt
This enables users to use the nice run method of `ChiselStage` with their own set of phases.
2019-10-21Merge pull request #1175 from freechipsproject/bore-nameSchuyler Eldridge
Internal BoringUtils.bore Bug Fix
2019-10-21Add BoringUtils.bore test for internal boringSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-21Fix BoringUtils.bore for internal boringSchuyler Eldridge
This fixes a bug where internal boring using BoringUtils.bore would fail because it was using instanceName which cannot be called before the module closes. Previously, this meant that BoringUtils.bore would work for boring instances (which are closed in a parent), but not for boring signals in the current, unclosed module. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-18Interval Data Type Support for Chisel (#1210)Chick Markley
Plan to be released with 3.3. Breaks experimental Range API. Adds new Interval type and associated support. This commit adds the following: - Renamed Range to IntervalRange to avoid name collision with scala Range - Changed RangeTransform macro to Return an IntervalRange - Improved error messages on missing comma or decimal - Added notational support for binary point - Some formatting cleanup also - SIntFactory - Change to use IntervalRange API - UIntFactory - UInt from range has custom width computation - It does not need to deal with lowerbound extending bit requirements - Code to handle special case of range"[0,0]" to have a width of 1 - IR.scala - Removed Bound and other constraint code that was duplicating firrtl stuff - Added new RangeType - Added IntervalRange class and object - RangeSpec - modified just a bit to handle notational differences - previous range interpolator returned tuple now returns IntervalRange - Add IntervalType to emitter - Added IntervalSpec with many tests - Added ScalaIntervalSimulatorSpec which tests golden model for Interval - Added ScalaIntervalSimulator which is a golden model for Interval - This gold may not have been polished to a high sheen - Add IntervalLit cases to Converter - Add Interval PrimOps to IR - asInterval, wrap, squz, clip, setp, decp, incp - Add IntervalLit class to IR - Add Interval to MonoConnect - Add Interval Type to Bits (in experimental package) - add conversions to Interval from other types - Add Interval clone stuff to Data - Add Literal creation helpers to chisel3 package - these may move to experimental if I can figure that out
2019-10-08Fix direction of dynamic index in complex Vec (#1196)Jack Koenig
Dynamically indexing a Vec of Flipped bidirectional Bundles would get the wrong directions on the elements of the Bundles Fixes #1192
2019-10-07Merge pull request #1194 from freechipsproject/issue-1166Schuyler Eldridge
Strip Object and Outer Class from desiredName
2019-10-07Improve desiredName for nested objects/classesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-30Bump sbt to 1.3.2 (#1188)Jim Lawson
2019-09-27Merge pull request #1193 from freechipsproject/readme-fixSchuyler Eldridge
More README.md fixes
2019-09-26More README.md fixesSchuyler Eldridge
- Scaladoc for "latest" is 2.11, so use a 2.11-style link - Use full path for SETUP.md - Switch migration guide to point to website version over wiki Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-25Merge pull request #1191 from freechipsproject/readme-fixSchuyler Eldridge
Use raw link for FIR filter
2019-09-25Use raw link for FIR filterSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-25Merge pull request #1190 from freechipsproject/readme-fixSchuyler Eldridge
Readme Fixes
2019-09-25Simplify data types README descriptionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-25Use full URL links for imagesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-25Add graphviz type hierarchy with built svg/pngSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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