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AgeCommit message (Expand)Author
2022-06-08Added migration for inferModuleReset (#2571) (#2573)mergify[bot]
2022-06-08Enhance suggestion in literal extract warning (#2569) (#2570)mergify[bot]
2022-06-07Add single argument Bits.extract (#2566) (#2568)mergify[bot]
2022-06-06Add --warn:reflective-naming (backport #2561) (#2565)mergify[bot]
2022-06-03Deprecate implicit .U() and .S() syntax for literal bit extracts (backport #2...mergify[bot]
2022-06-02Support VerificationStatement in the naming plugin (#2555) (#2557)mergify[bot]
2022-06-01Add formatted Printable interpolator `cf` (#2528) (#2553)mergify[bot]
2022-05-29Deprecate accessing the name of non-hardware Data (#2550) (#2552)mergify[bot]
2022-05-27Make ExtModule port naming consistent with Module (#2548) (#2549)mergify[bot]
2022-05-24Support Vecs of empty Bundles (#2543) (#2545)mergify[bot]
2022-05-19Support := views to DontCare (#2536) (#2539)mergify[bot]
2022-05-19Update experimental-features.md (#2537) (#2538)mergify[bot]
2022-05-14Deprecate named arguments for methods moving to macros in 3.6 (#2530)Jack Koenig
2022-05-13Update mimaPreviousArtifacts to 3.5.3 (#2529)Jack Koenig
2022-05-12Update CONTRIBUTING.md for backport cleanup process (backport #2523) (#2524)mergify[bot]
2022-05-12Support separately elaborating definition and instance in ChiselStage (backpo...mergify[bot]
2022-04-26Merge branch '3.5.x' into 3.5-releaseJack
2022-04-26Bump version strings.Jack
2022-04-26Fix spurious warning from Bundle plugin (#2506) (#2507)mergify[bot]
2022-04-25Fix error message for BlackBox without val io <: Record (#2504) (#2505)mergify[bot]
2022-04-25Fix warning injected into user code by @chiselName (#2500) (#2503)mergify[bot]
2022-04-20Generate a balanced tree with reduceTree (#2318) (#2499)mergify[bot]
2022-04-19Allow creating memories without an implicit clock (#2494) (#2495)mergify[bot]
2022-04-19verification: switch order of assert/assume and printf (#2484) (#2493)mergify[bot]
2022-04-18Fix small typos in doc comment (#2490) (#2492)mergify[bot]
2022-04-18Clarify example in Printable (#2454) (#2456)mergify[bot]
2022-04-15Enable Clock Invalidation (#2485) (#2487)mergify[bot]
2022-04-12Optimize memory use of naming prefixes (#2471) (#2480)mergify[bot]
2022-04-12Enhance views to [sometimes] support dynamic indexing and implement FlatIO (b...mergify[bot]
2022-04-05Micro-optimize Namespace.name (#2474) (#2475)mergify[bot]
2022-04-05Micro-optimize String building in _computeName (#2472) (#2473)mergify[bot]
2022-04-01Prevent FIRRTL bulk connects on BlackBox Bundles. (#2468) (#2469)mergify[bot]
2022-03-30Use var List instead of ListBuffer to save memory (#2465) (#2467)mergify[bot]
2022-03-25rm unused/deprecated BlackBoxResourceAnno import (#2458) (#2460)mergify[bot]
2022-03-15Merge branch '3.5.x' into 3.5-releaseJack
2022-03-15Bump version strings.Jack
2022-03-15[docs] Add Cookbook section on aliased Bundle fields (#2444) (#2448)mergify[bot]
2022-03-10Emit FIRRTL bulkconnects whenever possible (#2381) (#2440)mergify[bot]
2022-03-09Support BlackBoxes in D/I (#2438) (#2442)mergify[bot]
2022-03-08Add scanLeftOr and scanRightOr utilies (#2407) (#2437)mergify[bot]
2022-03-07Tweaks to the Verilog-vs-Chisel Page (#2432) (#2433)mergify[bot]
2022-03-04Add SVG Version of Bundle Example Diagram (#2425) (#2431)mergify[bot]
2022-03-04Issue errors on out-of-range extracts when width is known (#2428) (#2429)mergify[bot]
2022-03-03Add Verilog-chisel side by side Reference Page to Docs (#2323) (#2426)mergify[bot]
2022-02-15Make TruthTable accept unknown input width (#2387) (#2417)mergify[bot]
2022-02-11Hierarchy API: make Mems lookupable (#2404) (#2410)mergify[bot]
2022-02-10Make Tuple2 Lookupable (#2372) (#2406)mergify[bot]
2022-02-08Overload getVerilogString to accept arguments (#2401) (#2402)mergify[bot]
2022-02-08Merge branch '3.5.x' into 3.5-releaseJack
2022-02-08Bump version strings.Jack
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