Prevent FIRRTL bulk connects on BlackBox Bundles. (#2468) (#2469)

(cherry picked from commit 4da1e89f3a0b79adcb39ea5defb393ed6c00fa2f)

Co-authored-by: fzi-hielscher <47524191+fzi-hielscher@users.noreply.github.com>

2 files changed, 27 insertions, 1 deletions

diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala
index a8b425f5..2d6c9e4a 100644
--- a/core/src/main/scala/chisel3/internal/BiConnect.scala
+++ b/core/src/main/scala/chisel3/internal/BiConnect.scala
@@ -285,7 +285,13 @@ private[chisel3] object BiConnect {
       case _ => true
     }
 
-    typeCheck && contextCheck && bindingCheck && flow_check && sourceNotLiteralCheck
+    // do not bulk connect the 'io' pseudo-bundle of a BlackBox since it will be decomposed in FIRRTL
+    def blackBoxCheck = Seq(source, sink).map(_._parent).forall {
+      case Some(_: BlackBox) => false
+      case _ => true
+    }
+
+    typeCheck && contextCheck && bindingCheck && flow_check && sourceNotLiteralCheck && blackBoxCheck
   }
 
   // These functions (finally) issue the connection operation
diff --git a/src/test/scala/chiselTests/BulkConnectSpec.scala b/src/test/scala/chiselTests/BulkConnectSpec.scala
index 463122bd..281890d4 100644
--- a/src/test/scala/chiselTests/BulkConnectSpec.scala
+++ b/src/test/scala/chiselTests/BulkConnectSpec.scala
@@ -94,6 +94,26 @@ class BulkConnectSpec extends ChiselPropSpec {
     chirrtl should include("deq <= enq")
   }
 
+  property("Chisel connects should not emit a FIRRTL bulk connect for BlackBox IO Bundles") {
+    class MyBundle extends Bundle {
+      val O: Bool = Output(Bool())
+      val I: Bool = Input(Bool())
+    }
+
+    val chirrtl = ChiselStage.emitChirrtl(new Module {
+      val io: MyBundle = IO(Flipped(new MyBundle))
+
+      val bb = Module(new BlackBox {
+        val io: MyBundle = IO(Flipped(new MyBundle))
+      })
+
+      io <> bb.io
+    })
+    // There won't be a bb.io Bundle in FIRRTL, so connections have to be done element-wise
+    chirrtl should include("bb.O <= io.O")
+    chirrtl should include("io.I <= bb.I")
+  }
+
   property("MonoConnect should bulk connect undirectioned internal wires") {
     val chirrtl = ChiselStage.emitChirrtl(new Module {
       val io = IO(new Bundle {})