diff options
| author | mergify[bot] | 2022-05-19 18:32:30 +0000 |
|---|---|---|
| committer | GitHub | 2022-05-19 18:32:30 +0000 |
| commit | 7825b432ece7abee9c955f2429046d1c48222437 (patch) | |
| tree | e3d4768ab7d2c2e0134092ea7f0c8990deac7729 | |
| parent | 9b63c18f4654dfea54ce826df2c386aec4d8e1c2 (diff) | |
Support := views to DontCare (#2536) (#2539)
(cherry picked from commit 77a6c93592d5766d66f199720fc6d69478005091)
Co-authored-by: Jack Koenig <koenig@sifive.com>
| -rw-r--r-- | core/src/main/scala/chisel3/internal/MonoConnect.scala | 4 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/experimental/DataView.scala | 19 |
2 files changed, 22 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/internal/MonoConnect.scala b/core/src/main/scala/chisel3/internal/MonoConnect.scala index 40056c89..31364804 100644 --- a/core/src/main/scala/chisel3/internal/MonoConnect.scala +++ b/core/src/main/scala/chisel3/internal/MonoConnect.scala @@ -210,7 +210,9 @@ private[chisel3] object MonoConnect { } // Source is DontCare - it may be connected to anything. It generates a defInvalid for the sink. - case (sink, DontCare) => pushCommand(DefInvalid(sourceInfo, sink.lref)) + case (_sink: Element, DontCare) => + val sink = reify(_sink) // Handle views + pushCommand(DefInvalid(sourceInfo, sink.lref)) // DontCare as a sink is illegal. case (DontCare, _) => throw DontCareCantBeSink // Analog is illegal in mono connections. diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala index e7caacfd..ac8357f0 100644 --- a/src/test/scala/chiselTests/experimental/DataView.scala +++ b/src/test/scala/chiselTests/experimental/DataView.scala @@ -479,6 +479,25 @@ class DataViewSpec extends ChiselFlatSpec { (err.getMessage should fullyMatch).regex(expected) } + it should "support invalidation" in { + class MyModule extends Module { + val a, b, c, d, e, f = IO(Output(UInt(8.W))) + val foo = (a, b).viewAs + val bar = (c, d).viewAs + val fizz = (e, f).viewAs + foo := DontCare + bar <> DontCare + fizz._1 := DontCare + fizz._2 <> DontCare + } + + val chirrtl = ChiselStage.emitChirrtl(new MyModule) + val expected = ('a' to 'f').map(c => s"$c is invalid") + for (line <- expected) { + chirrtl should include(line) + } + } + behavior.of("PartialDataView") it should "still error if the mapping is non-total in the view" in { |
