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AgeCommit message (Expand)Author
2020-03-31Update sbt-site to 1.3.3 (#1340)Scala Steward
2020-03-30Java API Documents Linking (#1367)Schuyler Eldridge
2020-03-28Add pubishSettings to subprojects. (#1390)Jim Lawson
2020-03-26Bump to Scala 2.12.11 (#1389)Jack Koenig
2020-03-26Set StageError cause in ChiselStage (#1382)Schuyler Eldridge
2020-03-25Merge pull request #1384 from freechipsproject/no-more-compile-internalJack Koenig
2020-03-25Rename subprojects to more canonical namesJack Koenig
2020-03-25Remove compile-internal from build.sbtJack Koenig
2020-03-24Propagate user compile options for Chisel.Module (#1387)Jack Koenig
2020-03-24Merge pull request #1213 from freechipsproject/driver-deprecationsSchuyler Eldridge
2020-03-24Update README.md to reference ChiselStageSchuyler Eldridge
2020-03-24Add ChiselStageSpec for string/circuit emissionSchuyler Eldridge
2020-03-24Add helper methods to ChiselStage for Driver migrationSchuyler Eldridge
2020-03-24Deprecate Driver methods in favor of ChiselStageSchuyler Eldridge
2020-03-23Remove toNamed (and friends) deprecation. (#1377)Jim Lawson
2020-03-23Add NoChiselNamePrefix to ignore instances in @chiselName (#1383)Jack Koenig
2020-03-21Use innermost builder cause to trim stack trace (#1380)Schuyler Eldridge
2020-03-19Merge pull request #1374 from freechipsproject/dont-wrap-elaboration-annotationsSchuyler Eldridge
2020-03-19Add Scaladoc to ChiselExceptionSchuyler Eldridge
2020-03-19Safer generation of ChiselException.builderNameSchuyler Eldridge
2020-03-19Code style improvementSchuyler Eldridge
2020-03-19Test nested ChiselException in ChiselMainSchuyler Eldridge
2020-03-19Report trimmed stack trace of Builder causeSchuyler Eldridge
2020-03-11Wrap elaboration in ChiselExceptionSchuyler Eldridge
2020-03-10[mergify] Update match string for labeling backported PRs (#1373)Albert Magyar
2020-03-08Merge pull request #1372 from freechipsproject/mergify-ignore-bp-conflictsAlbert Magyar
2020-03-08Label & block conflicting backport PRsAlbert Magyar
2020-03-06Make mergify open backport PRs & signal on failed cherry-picksAlbert Magyar
2020-03-06Make implicit clock and reset final vals (#1360)Jack Koenig
2020-03-06Provide API to set concrete type of implicit reset (#1361)Jack Koenig
2020-03-02Cleanup aspects (#1359)Adam Izraelevitz
2020-02-28Retain default version assignment (#1365)Jim Lawson
2020-02-21mill: add testOnly (#1357)Sequencer
2020-02-21mill: sbt-compatible publishing (#1356)Sequencer
2020-02-19Merge pull request #1270 from freechipsproject/dependency-api-2Schuyler Eldridge
2020-02-19Migrate to Dependency WrapperSchuyler Eldridge
2020-02-19Patch fix #1109 (#1346)Jack Koenig
2020-02-19Upcoming Events: Remove CCC, add Dev Meetings (#1345)Schuyler Eldridge
2020-02-13Fix mill build (#1324)Sequencer
2020-02-12Fix := of Reset and AsyncReset to DontCare (#1336)Jack Koenig
2020-02-11Clone child elements lazily in Vec (#1329)Jack Koenig
2020-02-11Bump sbt and tool/plugin dependencies. (#1332)Jim Lawson
2020-02-10Make Queue.irrevocable work properly in chisel3Edward Wang
2020-02-10Printf: Add support for tabs, and give helpful error messages (#1323) (#1326)Jack Koenig
2020-02-08README: have a link to the classic tutorial (#1325)Martin Schoeberl
2020-02-06Merge pull request #1315 from freechipsproject/emit-orr-andrSchuyler Eldridge
2020-02-06Emit FIRRTL andr, orr for Bits.{andR, orR}Schuyler Eldridge
2020-02-05Add information about widths to RegNext (#1318)Schuyler Eldridge
2020-02-03Add read-under-write parameter to SyncReadMem (#1183)Albert Magyar
2020-02-03Merge pull request #1285 from freechipsproject/add-asbool-to-clockChick Markley
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