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2019-10-23Merge pull request #1216 from freechipsproject/non-private-ChiselStage-targetsSchuyler Eldridge
Make ChiselStage targets not private
2019-10-23Make ChiselStage targets not privateColin Schmidt
This enables users to use the nice run method of `ChiselStage` with their own set of phases.
2019-10-21Merge pull request #1175 from freechipsproject/bore-nameSchuyler Eldridge
Internal BoringUtils.bore Bug Fix
2019-10-21Add BoringUtils.bore test for internal boringSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-21Fix BoringUtils.bore for internal boringSchuyler Eldridge
This fixes a bug where internal boring using BoringUtils.bore would fail because it was using instanceName which cannot be called before the module closes. Previously, this meant that BoringUtils.bore would work for boring instances (which are closed in a parent), but not for boring signals in the current, unclosed module. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-18Interval Data Type Support for Chisel (#1210)Chick Markley
Plan to be released with 3.3. Breaks experimental Range API. Adds new Interval type and associated support. This commit adds the following: - Renamed Range to IntervalRange to avoid name collision with scala Range - Changed RangeTransform macro to Return an IntervalRange - Improved error messages on missing comma or decimal - Added notational support for binary point - Some formatting cleanup also - SIntFactory - Change to use IntervalRange API - UIntFactory - UInt from range has custom width computation - It does not need to deal with lowerbound extending bit requirements - Code to handle special case of range"[0,0]" to have a width of 1 - IR.scala - Removed Bound and other constraint code that was duplicating firrtl stuff - Added new RangeType - Added IntervalRange class and object - RangeSpec - modified just a bit to handle notational differences - previous range interpolator returned tuple now returns IntervalRange - Add IntervalType to emitter - Added IntervalSpec with many tests - Added ScalaIntervalSimulatorSpec which tests golden model for Interval - Added ScalaIntervalSimulator which is a golden model for Interval - This gold may not have been polished to a high sheen - Add IntervalLit cases to Converter - Add Interval PrimOps to IR - asInterval, wrap, squz, clip, setp, decp, incp - Add IntervalLit class to IR - Add Interval to MonoConnect - Add Interval Type to Bits (in experimental package) - add conversions to Interval from other types - Add Interval clone stuff to Data - Add Literal creation helpers to chisel3 package - these may move to experimental if I can figure that out
2019-10-08Fix direction of dynamic index in complex Vec (#1196)Jack Koenig
Dynamically indexing a Vec of Flipped bidirectional Bundles would get the wrong directions on the elements of the Bundles Fixes #1192
2019-10-07Merge pull request #1194 from freechipsproject/issue-1166Schuyler Eldridge
Strip Object and Outer Class from desiredName
2019-10-07Improve desiredName for nested objects/classesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-30Bump sbt to 1.3.2 (#1188)Jim Lawson
2019-09-27Merge pull request #1193 from freechipsproject/readme-fixSchuyler Eldridge
More README.md fixes
2019-09-26More README.md fixesSchuyler Eldridge
- Scaladoc for "latest" is 2.11, so use a 2.11-style link - Use full path for SETUP.md - Switch migration guide to point to website version over wiki Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-25Merge pull request #1191 from freechipsproject/readme-fixSchuyler Eldridge
Use raw link for FIR filter
2019-09-25Use raw link for FIR filterSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-25Merge pull request #1190 from freechipsproject/readme-fixSchuyler Eldridge
Readme Fixes
2019-09-25Simplify data types README descriptionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-25Use full URL links for imagesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-25Add graphviz type hierarchy with built svg/pngSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-25Use line instead of empty H1 in README.mdSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-19Add running one testcase to mill (#1103)Leway Colin
2019-09-17Updated to sbt 1.3.0 (#1181)Boris V.Kuznetsov
2019-09-16Da steve101 tree reduce (#485)Jack Koenig
* Add a tree reduce function to Vec * Change function names of reduce operation function in Vec * Change reference to single layer operation in Vec.reduce * Commint name change for pair macro * Remove pair, call not necessary and can just be used from grouped(2) and map * Changed to reduceTree, added default identity function for single reduce. * Change style of Vec.reduceTree and tests to chisel3 and canonical Scala style * Cleanup Vec initialization, implicitCompileOptions
2019-09-16Bump Scala to 2.12.10 (#1179)Jack Koenig
2019-09-13Add requirements to Queue class (#1176)Jack Koenig
FIRRTL barfs on negative and zero-sized memories
2019-09-13Fix Queue.apply for size 0 in chisel3._ code (#1177)Jack Koenig
2019-09-11Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)Jim Lawson
* Move dontTouch out of experimental package. * Move RawModule, MultiIOModule out of experimental. * Respond to comments - Move LagacyModule from experimental to internal. *NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions. * Fix up a few more imports.
2019-09-09Bump Scala in build.scJack Koenig
2019-09-09Bump Scala to 2.12.9Jack Koenig
2019-09-09Merge pull request #1174 from freechipsproject/fix-api-linkSchuyler Eldridge
Switch to new API links
2019-09-09Switch to new API linksSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-08Merge pull request #1173 from freechipsproject/issue-1169Schuyler Eldridge
Add Chisel Cheatsheet Latest Release Link
2019-09-08Add Chisel Cheatsheet Latest Release LinkSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-05Bump dependency versions (#1158)Jim Lawson
2019-08-28refactor out _Factory traits + address EOF WSKamyar Mohajerani
2019-08-28Refactor Element, Num, and Analog classes to their own files (no functional ↵Kamyar Mohajerani
changes)
2019-08-27Merge pull request #1160 from freechipsproject/issue-1159Schuyler Eldridge
Fix Stack Trace Trimming in Driver
2019-08-27Test stack trace trimming for ChiselStageSchuyler Eldridge
Use FIRRTL stage-style testing to check stdout printing without and with --full-stacktrace. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Enable --module command line argumentSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Move stack trimming from Driver to ChiselStageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Add test that stack trace trimming worksSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Remove stack trace trimming in Elaborate phaseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Add firrtlTests.Utils methodsSchuyler Eldridge
This adds methods for examining stdout/stderr and exit codes inside of a Scala program. This are pulled directly from firrtlTests, but we aren't currently publishing those anywhere that we can get at them. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-19Refactor: remove redundant code (#1152)Leway Colin
* Refactor: remove redundant code * Change to protected API * Remove type hierarchy
2019-08-15Merge pull request #1155 from freechipsproject/dependency-apiSchuyler Eldridge
Dependency API (take 2)
2019-08-13Use a PhaseManager for Driver internalsSchuyler Eldridge
Migrate Driver to use a PhaseManager to internally resolve Phase ordering. This requires the use of an identity node to adequately describe the necessary prerequisite/dependents. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-08-13Migrate ChiselStage to use the DependencyAPISchuyler Eldridge
Modifies ChiselStage to use a PhaseManager for Phase ordering. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-08-13Add Dependencies for Chisel PhasesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-08-13Add support for asynchronous reset (#1011)Jack Koenig
Adds new AsyncReset and "abstract" Reset types. Reset is inferred in FIRRTL to be either AsyncReset or Bool. The "reset type" of a register is set by the type of its reset signal: val asyncReset: AsyncReset = IO(Input(AsyncReset())) val syncReset: Bool = IO(Input(Bool())) val abstractReset: Reset = IO(Input(Reset())) val asyncReg = withReset(asyncReset) { RegInit(0.U) } val syncReg = withReset(syncReset) { RegInit(0.U) } val inferredReg = withReset(abstractReset) { RegInit(0.U) } AsyncReset can be cast to and from Bool. Whereas synchronous reset is equivalent to a mux in front of a flip-flop and thus can be driven by logic, asynchronous reset requires that the reset value is a constant. This is checked in FIRRTL. Inference of the concrete type of a Reset occurs based on the type the Reset's drivers. This inference is very simple, it is simple forward propagation of the type, but it allows for writing blocks and modules that are agnostic to the reset type. In particular, the implicit `reset` value in MultiIOModule and thus Module is now concretely an instance of Reset and thus will be inferred in FIRRTL.
2019-08-12Aspect-Oriented Programming for Chisel (#1077)Adam Izraelevitz
Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.
2019-08-12Merge pull request #1151 from colin4124/patch1Schuyler Eldridge
Remove "-Xcheckinit" from build.sc
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