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2019-03-28Make core.DontCare private to chisel3 (#1054)Jim Lawson
Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.
2019-03-26Try to eliminate JVM hang due to static initialization deadlock (#1053)Jim Lawson
2019-03-25Allow naming annotation to work outside builder context (#1051)Richard Lin
2019-03-25Check field referential equality in autoclonetype (#1047)Richard Lin
2019-03-23Aggregate coverage - aggregate tests but not publishing (#1040)Jim Lawson
Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml This should finally fix #772.
2019-03-23move doNotDedup to experimental (#1008)Sequencer
2019-03-22Add Record to type hierarchy documentationEdward Wang
2019-03-22Undeprecate isLit (#1048)Jack Koenig
2019-03-22Fix enum annotations (#936)Hasan Genc
* Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style
2019-03-21Remove @chiselName from MixedVec (#1045)Richard Lin
2019-03-21Change == to reference equality (eq) in Data print (#1044)Richard Lin
2019-03-20Replace textual release version with Shields SemVer badge. (#1043)Jim Lawson
* Replace textual release version with Shields SemVer badge. * Provide useful button action for release badge.
2019-03-20Mill support for Chisel3 (#1035)edwardcwang
Co-Authored-By: Jack Koenig <jack.koenig3@gmail.com> Co-Authored-By: Jim Lawson <ucbjrl@berkeley.edu>
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
* Update style warnings now that subprojects are aggregated. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml * Remove bogus tests that crept in with git add * Add missing import.
2019-03-15Merge pull request #1033 from freechipsproject/popcountAndrew Waterman
Tighten inferred width for PopCount
2019-03-15Merge branch 'master' into popcountedwardcwang
2019-03-15Fix typo in linkedwardcwang
2019-03-15Merge branch 'master' into popcountedwardcwang
2019-03-15Use TransitName for improved Pipe naming (#1024)Schuyler Eldridge
This changes from using the chiselname annotation on Pipe.apply to using an explicit TransitName. This results in an improved name for created valid and bits registers. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-03-15Fix PopCount widthAndrew Waterman
2019-03-15Add width constraint to PopCount test (which currently fails)Andrew Waterman
2019-03-15Add PopCount testAndrew Waterman
2019-03-14Decouple implementation details from LoadMemoryAnnotation. (#1034)Jim Lawson
2019-03-13Update recommended verilator version to 4.006 (#1032)Jim Lawson
2019-03-11ScalaDocs improvement for utils Math, MixedVec (#1019)Richard Lin
2019-02-25Docs for ListLookup (#1028)Richard Lin
Co-Authored-By: ducky64 <elpato25@gmail.com> Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@gmail.com> Co-Authored-By: Edward Wang <edward.c.wang@compdigitec.com>
2019-02-20Update templates to include documentation. (#1026)Paul Rigge
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
* Add HasBlackBoxPath trait * Use 'setResource' instead of 'addResource' * Add ScalaDoc
2019-02-19ScalaDoc for Mux (examples added) (#1014)Martin Schoeberl
Co-Authored-By: schoeberl <martin@jopdesign.com> Co-Authored-By: Edward Wang <edward.c.wang@compdigitec.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Update README to reference the bootcamp (#1025)Paul Rigge
* Update README to reference the bootcamp * Place learning section higher
2019-02-19Merge pull request #1017 from freechipsproject/scaladoc-TransitNameSchuyler Eldridge
- Add Scaladoc for chisel3.util.TransitName - Add test for TransitName
2019-02-19Add TransitNameSpecSchuyler Eldridge
This adds a test of chisel3.util.TransitName (which is used for the TransitName documentation). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Add Scaladoc for chisel3.util.TransitNameSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Mainline Chisel multi-clock functionality (#1013)edwardcwang
Close #1009
2019-02-19Util doc lsfr (#1021)Chick Markley
* Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Fixed typos in LFSR - Reduce trials a little - Add test of LFSR period * Update documentation for LSFR16 - Fixed remaining LSFR, arrgh - Removed intellij specific warning suppressor - Fixed comments/scaladoc wording and case. * Update documentation for LSFR16 - Use printable interpolator as example of printing out a Vec
2019-02-19Documentation for Reg utilities (#1018)Martin Schoeberl
2019-02-19ScalaDoc for OneHot (#1016)Martin Schoeberl
2019-02-19Merge pull request #1023 from freechipsproject/scaladoc-ValidSchuyler Eldridge
Valid/Pipe Improvements: Scaladoc, latency requirement
2019-02-18Add requirement that Pipe latency >= 0Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-18Add Scaladoc for chisel3.util.PipeSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-18Add Scaldoc for chisel3.util.ValidSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-01Queue TestsBrendan Sweeney
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-23Use Verilator 4.006; bump to Scala 2.12.7 (#947)Jim Lawson
Now that ucbbar/chisel3-tools has Verilator 4.006, use that for tests.
2019-01-23Bump copyright year (#997)Jim Lawson
2019-01-22Import aliases for chisel3.core (#998)Richard Lin
Compatibility for rename introduced by #994
2019-01-22Define Data .toString (#985)Richard Lin
toString on Data subtypes will now print the type and optionally binding information including literals and IO names as feasible.
2019-01-22Remove ghpages (#992)Jim Lawson
* Remove GhpagesPlugin. (#966) * Restore old SCM reference (after removing ghpages)
2019-01-22Merge pull request #978 from seldridge/boring-utils-dedup-fixSchuyler Eldridge
- Fix BoringUtils deduplication bug, include new tests - Update/clarify BoringUtils scaladoc
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
This compresses the Scaladoc for BoringUtils slightly by using 120 character lines and removing unnecessary whitespace. This also changes the poorly named "dedup" parameter to the what it actually is: "disableDedup". Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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