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AgeCommit message (Expand)Author
2019-03-28Make core.DontCare private to chisel3 (#1054)Jim Lawson
2019-03-26Try to eliminate JVM hang due to static initialization deadlock (#1053)Jim Lawson
2019-03-25Allow naming annotation to work outside builder context (#1051)Richard Lin
2019-03-25Check field referential equality in autoclonetype (#1047)Richard Lin
2019-03-23Aggregate coverage - aggregate tests but not publishing (#1040)Jim Lawson
2019-03-23move doNotDedup to experimental (#1008)Sequencer
2019-03-22Add Record to type hierarchy documentationEdward Wang
2019-03-22Undeprecate isLit (#1048)Jack Koenig
2019-03-22Fix enum annotations (#936)Hasan Genc
2019-03-21Remove @chiselName from MixedVec (#1045)Richard Lin
2019-03-21Change == to reference equality (eq) in Data print (#1044)Richard Lin
2019-03-20Replace textual release version with Shields SemVer badge. (#1043)Jim Lawson
2019-03-20Mill support for Chisel3 (#1035)edwardcwang
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
2019-03-15Merge pull request #1033 from freechipsproject/popcountAndrew Waterman
2019-03-15Merge branch 'master' into popcountedwardcwang
2019-03-15Fix typo in linkedwardcwang
2019-03-15Merge branch 'master' into popcountedwardcwang
2019-03-15Use TransitName for improved Pipe naming (#1024)Schuyler Eldridge
2019-03-15Fix PopCount widthAndrew Waterman
2019-03-15Add width constraint to PopCount test (which currently fails)Andrew Waterman
2019-03-15Add PopCount testAndrew Waterman
2019-03-14Decouple implementation details from LoadMemoryAnnotation. (#1034)Jim Lawson
2019-03-13Update recommended verilator version to 4.006 (#1032)Jim Lawson
2019-03-11ScalaDocs improvement for utils Math, MixedVec (#1019)Richard Lin
2019-02-25Docs for ListLookup (#1028)Richard Lin
2019-02-20Update templates to include documentation. (#1026)Paul Rigge
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
2019-02-19ScalaDoc for Mux (examples added) (#1014)Martin Schoeberl
2019-02-19Update README to reference the bootcamp (#1025)Paul Rigge
2019-02-19Merge pull request #1017 from freechipsproject/scaladoc-TransitNameSchuyler Eldridge
2019-02-19Add TransitNameSpecSchuyler Eldridge
2019-02-19Add Scaladoc for chisel3.util.TransitNameSchuyler Eldridge
2019-02-19Mainline Chisel multi-clock functionality (#1013)edwardcwang
2019-02-19Util doc lsfr (#1021)Chick Markley
2019-02-19Documentation for Reg utilities (#1018)Martin Schoeberl
2019-02-19ScalaDoc for OneHot (#1016)Martin Schoeberl
2019-02-19Merge pull request #1023 from freechipsproject/scaladoc-ValidSchuyler Eldridge
2019-02-18Add requirement that Pipe latency >= 0Schuyler Eldridge
2019-02-18Add Scaladoc for chisel3.util.PipeSchuyler Eldridge
2019-02-18Add Scaldoc for chisel3.util.ValidSchuyler Eldridge
2019-02-01Queue TestsBrendan Sweeney
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-23Use Verilator 4.006; bump to Scala 2.12.7 (#947)Jim Lawson
2019-01-23Bump copyright year (#997)Jim Lawson
2019-01-22Import aliases for chisel3.core (#998)Richard Lin
2019-01-22Define Data .toString (#985)Richard Lin
2019-01-22Remove ghpages (#992)Jim Lawson
2019-01-22Merge pull request #978 from seldridge/boring-utils-dedup-fixSchuyler Eldridge
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
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