7 files changed, 12 insertions, 11 deletions
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index bef56a56..d2e42fa9 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -14,9 +14,9 @@ class Coord extends Bundle {
 class BundleWire(n: Int) extends Module {
   val io = new Bundle {
     val in   = (new Coord).asInput
-    val outs = Vec(new Coord, n).asOutput
+    val outs = Vec(n, new Coord).asOutput
   }
-  val coords = Wire(Vec(new Coord, n))
+  val coords = Wire(Vec(n, new Coord))
   for (i <- 0 until n) {
     coords(i)  := io.in
     io.outs(i) := coords(i)
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 27fd5125..88ba795b 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -15,8 +15,8 @@ class PlusOne extends Module {
 
 class ModuleVec(val n: Int) extends Module {
   val io = new Bundle {
-    val ins  = Vec(UInt(INPUT,  32), n)
-    val outs = Vec(UInt(OUTPUT, 32), n)
+    val ins  = Vec(n, UInt(INPUT,  32))
+    val outs = Vec(n, UInt(OUTPUT, 32))
   }
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 93a2c39f..999b7d36 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -9,8 +9,8 @@ class Padder extends Module {
     val asp = SInt(OUTPUT, 8)
     val aup = UInt(OUTPUT, 8)
   }
-  io.asp := io.a.toSInt
-  io.aup := io.a.toUInt
+  io.asp := io.a.asSInt
+  io.aup := io.a.asUInt
 }
 
 /*
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index ad5cf762..3daa5bd2 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -12,8 +12,9 @@ class Risc extends Module {
     val valid  = Bool(OUTPUT)
     val out    = Bits(OUTPUT, 32)
   }
-  val file = Mem(Bits(width = 32), 256)
-  val code = Mem(Bits(width = 32), 256)
+  val memSize = 256
+  val file = Mem(memSize, Bits(width = 32))
+  val code = Mem(memSize, Bits(width = 32))
   val pc   = Reg(init=UInt(0, 8))
 
   val add_op :: imm_op :: Nil = Enum(Bits(width = 8), 2)
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 600934aa..ac799c8a 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -13,7 +13,7 @@ class ChiselStack(val depth: Int) extends Module {
     val dataOut = UInt(OUTPUT, 32)
   }
 
-  val stack_mem = Mem(UInt(width = 32), depth)
+  val stack_mem = Mem(depth, UInt(width = 32))
   val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
   val out       = Reg(init = UInt(0, width = 32))
 
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 7ffa24ed..c79eb8a4 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -15,7 +15,7 @@ class Tbl(w: Int, n: Int) extends Module {
     val  d  = UInt(INPUT, w)
     val  o  = UInt(OUTPUT, w)
   }
-  val m = Mem(UInt(width = w), n)
+  val m = Mem(n, UInt(width = w))
   io.o := m(io.ri)
   when (io.we) {
     m(io.wi) := io.d
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index f48c1b63..5239c6ba 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -29,7 +29,7 @@ class TabulateTester(n: Int) extends BasicTester {
 
 class ShiftRegisterTester(n: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), n*2)
-  val shifter = Reg(Vec(UInt(width = log2Up(n)), n))
+  val shifter = Reg(Vec(n, UInt(width = log2Up(n))))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
   when (cnt >= UInt(n)) {