1 files changed, 12 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala
index 176ea5e7..ebdb1483 100644
--- a/src/test/scala/chiselTests/Mem.scala
+++ b/src/test/scala/chiselTests/Mem.scala
@@ -93,4 +93,16 @@ class MemorySpec extends ChiselPropSpec {
     val cmem = compile(new HugeCMemTester(size))
     cmem should include (s"reg /* sparse */ [7:0] mem [0:$addrWidth'd${size-1}];")
   }
+
+  property("Implicit conversions with Mem indices should work") {
+    """
+    |import chisel3._
+    |import chisel3.util.ImplicitConversions._
+    |class MyModule extends Module {
+    |  val io = IO(new Bundle {})
+    |  val mem = Mem(32, UInt(8.W))
+    |  mem(0) := 0.U
+    |}
+    |""".stripMargin should compile
+  }
 }