2 files changed, 24 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index d9fab09a..d44178ad 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -45,6 +45,10 @@ object Mem {
     pushCommand(DefMemory(sourceInfo, mem, mt, size))
     mem
   }
+
+  /** @group SourceInfoTransformMacro */
+  def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Mem[T] =
+    do_apply(BigInt(size), t)(sourceInfo, compileOptions)
 }
 
 sealed abstract class MemBase[T <: Data](t: T, val length: BigInt) extends HasId with NamedComponent with SourceInfoDoc {
@@ -66,6 +70,10 @@ sealed abstract class MemBase[T <: Data](t: T, val length: BigInt) extends HasId
     apply(idx.asUInt)
   }
 
+  /** @group SourceInfoTransformMacro */
+  def do_apply(idx: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T =
+    do_apply(BigInt(idx))(sourceInfo, compileOptions)
+
   /** Creates a read/write accessor into the memory with dynamic addressing.
     * See the class documentation of the memory for more detailed information.
     */
@@ -175,6 +183,10 @@ object SyncReadMem {
     pushCommand(DefSeqMemory(sourceInfo, mem, mt, size))
     mem
   }
+
+  /** @group SourceInfoTransformMacro */
+  def do_apply[T <: Data](size: Int, t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SyncReadMem[T] =
+    do_apply(BigInt(size), t)(sourceInfo, compileOptions)
 }
 
 /** A sequential/synchronous-read, sequential/synchronous-write memory.
diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala
index 176ea5e7..ebdb1483 100644
--- a/src/test/scala/chiselTests/Mem.scala
+++ b/src/test/scala/chiselTests/Mem.scala
@@ -93,4 +93,16 @@ class MemorySpec extends ChiselPropSpec {
     val cmem = compile(new HugeCMemTester(size))
     cmem should include (s"reg /* sparse */ [7:0] mem [0:$addrWidth'd${size-1}];")
   }
+
+  property("Implicit conversions with Mem indices should work") {
+    """
+    |import chisel3._
+    |import chisel3.util.ImplicitConversions._
+    |class MyModule extends Module {
+    |  val io = IO(new Bundle {})
+    |  val mem = Mem(32, UInt(8.W))
+    |  mem(0) := 0.U
+    |}
+    |""".stripMargin should compile
+  }
 }