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Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/chiselTests/CompatibilitySpec.scala (renamed from src/test/scala/chiselTests/CompatibiltySpec.scala) | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/CompatibiltySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index cc14be5e..f3934f76 100644 --- a/src/test/scala/chiselTests/CompatibiltySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -161,6 +161,14 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks elaborate { new Chisel2CompatibleRisc } } + it should "not try to assign directions to Analog" in { + elaborate(new Module { + val io = new Bundle { + val port = chisel3.experimental.Analog(32.W) + } + }) + } + class SmallBundle extends Bundle { val f1 = UInt(width = 4) |