diff options
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Data.scala | 9 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/CompatibilitySpec.scala (renamed from src/test/scala/chiselTests/CompatibiltySpec.scala) | 8 |
2 files changed, 13 insertions, 4 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala index 74e41895..66f16294 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala @@ -202,10 +202,11 @@ abstract class Data extends HasId { * DO NOT USE OUTSIDE THIS PURPOSE. THIS OPERATION IS DANGEROUS! */ private[core] def _assignCompatibilityExplicitDirection: Unit = { - _userDirection match { - case UserDirection.Unspecified => _userDirection = UserDirection.Output - case UserDirection.Flip => _userDirection = UserDirection.Input - case UserDirection.Input | UserDirection.Output => // nothing to do + (this, _userDirection) match { + case (_: Analog, _) => // nothing to do + case (_, UserDirection.Unspecified) => _userDirection = UserDirection.Output + case (_, UserDirection.Flip) => _userDirection = UserDirection.Input + case (_, UserDirection.Input | UserDirection.Output) => // nothing to do } } diff --git a/src/test/scala/chiselTests/CompatibiltySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index cc14be5e..f3934f76 100644 --- a/src/test/scala/chiselTests/CompatibiltySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -161,6 +161,14 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks elaborate { new Chisel2CompatibleRisc } } + it should "not try to assign directions to Analog" in { + elaborate(new Module { + val io = new Bundle { + val port = chisel3.experimental.Analog(32.W) + } + }) + } + class SmallBundle extends Bundle { val f1 = UInt(width = 4) |