diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 6 | ||||
| -rw-r--r-- | src/main/scala/Chisel/utils.scala | 5 |
2 files changed, 8 insertions, 3 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index a3483c82..ee78b583 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -278,7 +278,9 @@ abstract class Data(dirArg: Direction) extends Id { private[Chisel] def lref: Alias = Alias(this) private[Chisel] def ref: Arg = if (isLit) litArg() else lref private[Chisel] def debugName = mod.debugName + "." + getRefForId(this).debugName - private[Chisel] def cloneTypeWidth(width: Int): this.type + private[Chisel] def cloneTypeWidth(width: Int): this.type // deprecated + private[Chisel] def cloneTypeWidth(width: Option[Int]): this.type = + cloneTypeWidth(width.getOrElse(-1)) def := (that: Data): Unit = this badConnect that def <> (that: Data): Unit = this badConnect that @@ -931,7 +933,7 @@ class Bundle extends Aggregate(NO_DIR) { BundleType(this.toPorts, isFlip) override def flatten: IndexedSeq[Bits] = - allElts.map(_._2.flatten).reduce(_ ++ _) + allElts.flatMap(_._2.flatten) lazy val elements: ListMap[String, Data] = ListMap(allElts:_*) diff --git a/src/main/scala/Chisel/utils.scala b/src/main/scala/Chisel/utils.scala index b0255ef9..b1e6eb20 100644 --- a/src/main/scala/Chisel/utils.scala +++ b/src/main/scala/Chisel/utils.scala @@ -94,7 +94,10 @@ object Mux1H if (in.tail.isEmpty) in.head._2 else { val masked = in map {case (s, i) => Mux(s, i.toBits, Bits(0))} - in.head._2.fromBits(masked.reduceLeft(_|_)) + val width = + if (in.forall(_._2.knownWidth)) Some(in.map(_._2.getWidth).max) + else None + in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_)) } } def apply[T <: Data](sel: UInt, in: Seq[T]): T = |