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Diffstat (limited to 'src/main/scala/Chisel/utils.scala')
| -rw-r--r-- | src/main/scala/Chisel/utils.scala | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/utils.scala b/src/main/scala/Chisel/utils.scala index b0255ef9..b1e6eb20 100644 --- a/src/main/scala/Chisel/utils.scala +++ b/src/main/scala/Chisel/utils.scala @@ -94,7 +94,10 @@ object Mux1H if (in.tail.isEmpty) in.head._2 else { val masked = in map {case (s, i) => Mux(s, i.toBits, Bits(0))} - in.head._2.fromBits(masked.reduceLeft(_|_)) + val width = + if (in.forall(_._2.knownWidth)) Some(in.map(_._2.getWidth).max) + else None + in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_)) } } def apply[T <: Data](sel: UInt, in: Seq[T]): T = |