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-rw-r--r--src/test/scala/chiselTests/AnalogSpec.scala4
-rw-r--r--src/test/scala/chiselTests/BetterNamingTests.scala10
-rw-r--r--src/test/scala/chiselTests/DontTouchSpec.scala2
-rw-r--r--src/test/scala/chiselTests/EnumSpec.scala2
-rw-r--r--src/test/scala/chiselTests/IOCompatibility.scala2
-rw-r--r--src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala4
-rw-r--r--src/test/scala/chiselTests/Module.scala6
-rw-r--r--src/test/scala/chiselTests/MultiClockSpec.scala2
-rw-r--r--src/test/scala/chiselTests/OneHotMuxSpec.scala16
-rw-r--r--src/test/scala/chiselTests/PrintableSpec.scala6
-rw-r--r--src/test/scala/chiselTests/TesterDriverSpec.scala2
-rw-r--r--src/test/scala/chiselTests/Vec.scala12
-rw-r--r--src/test/scala/examples/ImplicitStateVendingMachine.scala2
-rw-r--r--src/test/scala/examples/VendingMachineGenerator.scala2
14 files changed, 36 insertions, 36 deletions
diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala
index c2dee4a9..d4769f41 100644
--- a/src/test/scala/chiselTests/AnalogSpec.scala
+++ b/src/test/scala/chiselTests/AnalogSpec.scala
@@ -118,7 +118,7 @@ class AnalogSpec extends ChiselFlatSpec {
it should "NOT be connectable to UInts" in {
a [Exception] should be thrownBy {
runTester { new BasicTester {
- val uint = Wire(init = 0.U(32.W))
+ val uint = WireInit(0.U(32.W))
val sint = Wire(Analog(32.W))
sint := uint
}}
@@ -179,7 +179,7 @@ class AnalogSpec extends ChiselFlatSpec {
it should "work with blackboxes at different levels of the module hierarchy" in {
assertTesterPasses(new AnalogTester {
val mods = Seq(Module(new AnalogReaderBlackBox), Module(new AnalogReaderWrapper))
- val busWire = Wire(writer.io.bus)
+ val busWire = Wire(writer.io.bus.cloneType)
attach(writer.io.bus, mods(0).io.bus, mods(1).io.bus)
mods.foreach(check(_))
}, Seq("/chisel3/AnalogBlackBox.v"))
diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala
index a660086f..41b8eef3 100644
--- a/src/test/scala/chiselTests/BetterNamingTests.scala
+++ b/src/test/scala/chiselTests/BetterNamingTests.scala
@@ -26,12 +26,12 @@ class PerNameIndexing(count: Int) extends NamedModuleTester {
// Note this only checks Iterable[Chisel.Data] which excludes Maps
class IterableNaming extends NamedModuleTester {
val seq = Seq.tabulate(3) { i =>
- Seq.tabulate(2) { j => expectName(Wire(init = (i * j).U), s"seq_${i}_${j}") }
+ Seq.tabulate(2) { j => expectName(WireInit((i * j).U), s"seq_${i}_${j}") }
}
- val optSet = Some(Set(expectName(Wire(init = 0.U), "optSet_0"),
- expectName(Wire(init = 1.U), "optSet_1"),
- expectName(Wire(init = 2.U), "optSet_2"),
- expectName(Wire(init = 3.U), "optSet_3")))
+ val optSet = Some(Set(expectName(WireInit(0.U), "optSet_0"),
+ expectName(WireInit(1.U), "optSet_1"),
+ expectName(WireInit(2.U), "optSet_2"),
+ expectName(WireInit(3.U), "optSet_3")))
val stack = mutable.Stack[Module]()
for (i <- 0 until 4) {
diff --git a/src/test/scala/chiselTests/DontTouchSpec.scala b/src/test/scala/chiselTests/DontTouchSpec.scala
index 6cd2c54d..9a4e6660 100644
--- a/src/test/scala/chiselTests/DontTouchSpec.scala
+++ b/src/test/scala/chiselTests/DontTouchSpec.scala
@@ -26,7 +26,7 @@ class HasDeadCode(withDontTouch: Boolean) extends Module {
val inst = Module(new HasDeadCodeChild(withDontTouch))
inst.io.a := io.a
io.b := inst.io.b
- val dead = Wire(init = io.a + 1.U)
+ val dead = WireInit(io.a + 1.U)
if (withDontTouch) {
dontTouch(dead)
}
diff --git a/src/test/scala/chiselTests/EnumSpec.scala b/src/test/scala/chiselTests/EnumSpec.scala
index 37bbe2ff..e0069060 100644
--- a/src/test/scala/chiselTests/EnumSpec.scala
+++ b/src/test/scala/chiselTests/EnumSpec.scala
@@ -11,7 +11,7 @@ class EnumSpec extends ChiselFlatSpec {
"1-entry Enums" should "work" in {
assertTesterPasses(new BasicTester {
val onlyState :: Nil = Enum(1)
- val wire = Wire(init = onlyState)
+ val wire = WireInit(onlyState)
chisel3.assert(wire === onlyState)
stop()
})
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index 521e895d..28058963 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -21,7 +21,7 @@ class IOCModuleVec(val n: Int) extends Module {
val ins = Vec(n, Input(UInt(32.W)))
val outs = Vec(n, Output(UInt(32.W)))
})
- val pluses = Vec.fill(n){ Module(new IOCPlusOne).io }
+ val pluses = VecInit(Seq.fill(n){ Module(new IOCPlusOne).io })
for (i <- 0 until n) {
pluses(i).in := io.ins(i)
io.outs(i) := pluses(i).out
diff --git a/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala b/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala
index 52ca418a..43f2b0fd 100644
--- a/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala
+++ b/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala
@@ -22,9 +22,9 @@ class MissingCloneBindingExceptionSpec extends ChiselFlatSpec with Matchers {
class TestTop extends Module {
val io = IO(new Bundle {})
- val subs = Vec.fill(2) {
+ val subs = VecInit(Seq.fill(2) {
Module(new Test).io
- }
+ })
}
elaborate(new TestTop)
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 2ae8fa5e..432cd278 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -16,10 +16,10 @@ class PlusOne extends Module {
class ModuleVec(val n: Int) extends Module {
val io = IO(new Bundle {
- val ins = Input(Vec(n, 32.U))
- val outs = Output(Vec(n, 32.U))
+ val ins = Input(Vec(n, UInt(32.W)))
+ val outs = Output(Vec(n, UInt(32.W)))
})
- val pluses = Vec.fill(n){ Module(new PlusOne).io }
+ val pluses = VecInit(Seq.fill(n){ Module(new PlusOne).io })
for (i <- 0 until n) {
pluses(i).in := io.ins(i)
io.outs(i) := pluses(i).out
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 3f9ad895..7886649f 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -54,7 +54,7 @@ class MultiClockSubModuleTest extends BasicTester {
/** Test withReset changing the reset of a Reg */
class WithResetTest extends BasicTester {
- val reset2 = Wire(init = false.B)
+ val reset2 = WireInit(false.B)
val reg = withReset(reset2 || reset.toBool) { RegInit(0.U(8.W)) }
reg := reg + 1.U
diff --git a/src/test/scala/chiselTests/OneHotMuxSpec.scala b/src/test/scala/chiselTests/OneHotMuxSpec.scala
index c2efb6f8..9495703d 100644
--- a/src/test/scala/chiselTests/OneHotMuxSpec.scala
+++ b/src/test/scala/chiselTests/OneHotMuxSpec.scala
@@ -126,10 +126,10 @@ object Agg1 extends HasMakeLit[Agg1] {
val (d: Double, e: Double, f: Double, g: Double) = (x, x * 2.0, x * 3.0, x * 4.0)
val w = Wire(new Agg1)
- w.v(0) := Wire(d.F(4.BP))
- w.v(1) := Wire(e.F(4.BP))
- w.a.f1 := Wire(f.F(3.BP))
- w.a.f2 := Wire(g.F(5.BP))
+ w.v(0) := d.F(4.BP)
+ w.v(1) := e.F(4.BP)
+ w.a.f1 := f.F(3.BP)
+ w.a.f2 := g.F(5.BP)
w
}
}
@@ -147,10 +147,10 @@ object Agg2 extends HasMakeLit[Agg2] {
val (d: Double, e: Double, f: Double, g: Double) = (x, x * 2.0, x * 3.0, x * 4.0)
val w = Wire(new Agg2)
- w.v(0) := Wire(d.F(4.BP))
- w.v(1) := Wire(e.F(4.BP))
- w.a.f1 := Wire(f.F(3.BP))
- w.a.f2 := Wire(g.F(5.BP))
+ w.v(0) := d.F(4.BP)
+ w.v(1) := e.F(4.BP)
+ w.a.f1 := f.F(3.BP)
+ w.a.f2 := g.F(5.BP)
w
}
}
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
index 5f58429e..d733ab8c 100644
--- a/src/test/scala/chiselTests/PrintableSpec.scala
+++ b/src/test/scala/chiselTests/PrintableSpec.scala
@@ -67,7 +67,7 @@ class PrintableSpec extends FlatSpec with Matchers {
}
it should "generate proper printf for simple Decimal printing" in {
class MyModule extends BasicTester {
- val myWire = Wire(init = 1234.U)
+ val myWire = WireInit(1234.U)
printf(p"myWire = ${Decimal(myWire)}")
}
val firrtl = Driver.emit(() => new MyModule)
@@ -144,8 +144,8 @@ class PrintableSpec extends FlatSpec with Matchers {
}
it should "print UInts and SInts as Decimal by default" in {
class MyModule extends BasicTester {
- val myUInt = Wire(init = 0.U)
- val mySInt = Wire(init = -1.S)
+ val myUInt = WireInit(0.U)
+ val mySInt = WireInit(-1.S)
printf(p"$myUInt & $mySInt")
}
val firrtl = Driver.emit(() => new MyModule)
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index e32368e9..f3cf3bca 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -21,7 +21,7 @@ class FinishTester extends BasicTester {
stop()
}
- val test_wire = Wire(init=1.U(test_wire_width.W))
+ val test_wire = WireInit(1.U(test_wire_width.W))
// though we just set test_wire to 1, the assert below will pass because
// the finish will change its value
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index df2d6ec0..9b8855c4 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -12,7 +12,7 @@ class LitTesterMod(vecSize: Int) extends Module {
val io = IO(new Bundle {
val out = Output(Vec(vecSize, UInt()))
})
- io.out := Vec(Seq.fill(vecSize){0.U})
+ io.out := VecInit(Seq.fill(vecSize){0.U})
}
class RegTesterMod(vecSize: Int) extends Module {
@@ -36,7 +36,7 @@ class OneBitUnitRegVec extends Module {
val io = IO(new Bundle {
val out = Output(UInt(1.W))
})
- val oneBitUnitRegVec = Reg(Vec(1, 1.U))
+ val oneBitUnitRegVec = Reg(Vec(1, UInt(1.W)))
oneBitUnitRegVec(0) := 1.U(1.W)
io.out := oneBitUnitRegVec(0)
}
@@ -78,8 +78,8 @@ class IOTesterModFill(vecSize: Int) extends Module {
// This should generate a BindingException when we attempt to wire up the Vec.fill elements
// since they're pure types and hence unsynthesizeable.
val io = IO(new Bundle {
- val in = Input(Vec.fill(vecSize) {UInt()})
- val out = Output(Vec.fill(vecSize) {UInt()})
+ val in = Input(VecInit(Seq.fill(vecSize) {UInt()}))
+ val out = Output(VecInit(Seq.fill(vecSize) {UInt()}))
})
io.out := io.in
}
@@ -147,7 +147,7 @@ class ZeroEntryVecTester extends BasicTester {
val m = Module(new Module {
val io = IO(Output(bundleWithZeroEntryVec.cloneType))
})
- Wire(init = m.io.bar)
+ WireInit(m.io.bar)
stop()
}
@@ -171,7 +171,7 @@ class PassthroughModuleTester extends Module {
class ModuleIODynamicIndexTester(n: Int) extends BasicTester {
- val duts = Vec.fill(n)(Module(new PassthroughModule).io)
+ val duts = VecInit(Seq.fill(n)(Module(new PassthroughModule).io))
val tester = Module(new PassthroughModuleTester)
val (cycle, done) = Counter(true.B, n)
diff --git a/src/test/scala/examples/ImplicitStateVendingMachine.scala b/src/test/scala/examples/ImplicitStateVendingMachine.scala
index 06b0717e..92f57854 100644
--- a/src/test/scala/examples/ImplicitStateVendingMachine.scala
+++ b/src/test/scala/examples/ImplicitStateVendingMachine.scala
@@ -9,7 +9,7 @@ import chisel3._
class ImplicitStateVendingMachine extends SimpleVendingMachine {
// We let the value of nickel be 1 and dime be 2 for efficiency reasons
val value = RegInit(0.asUInt(3.W))
- val incValue = Wire(init = 0.asUInt(3.W))
+ val incValue = WireInit(0.asUInt(3.W))
val doDispense = value >= 4.U // 4 * nickel as 1 == $0.20
when (doDispense) {
diff --git a/src/test/scala/examples/VendingMachineGenerator.scala b/src/test/scala/examples/VendingMachineGenerator.scala
index 3b039c97..55a17d9f 100644
--- a/src/test/scala/examples/VendingMachineGenerator.scala
+++ b/src/test/scala/examples/VendingMachineGenerator.scala
@@ -54,7 +54,7 @@ class VendingMachineGenerator(
val width = log2Ceil(maxValue + 1).W
val value = RegInit(0.asUInt(width))
- val incValue = Wire(init = 0.asUInt(width))
+ val incValue = WireInit(0.asUInt(width))
val doDispense = value >= (sodaCost / minCoin).U
when (doDispense) {
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 17:12:09 +0000