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Diffstat (limited to 'src/test/scala/chiselTests/AnalogSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/AnalogSpec.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala index c2dee4a9..d4769f41 100644 --- a/src/test/scala/chiselTests/AnalogSpec.scala +++ b/src/test/scala/chiselTests/AnalogSpec.scala @@ -118,7 +118,7 @@ class AnalogSpec extends ChiselFlatSpec { it should "NOT be connectable to UInts" in { a [Exception] should be thrownBy { runTester { new BasicTester { - val uint = Wire(init = 0.U(32.W)) + val uint = WireInit(0.U(32.W)) val sint = Wire(Analog(32.W)) sint := uint }} @@ -179,7 +179,7 @@ class AnalogSpec extends ChiselFlatSpec { it should "work with blackboxes at different levels of the module hierarchy" in { assertTesterPasses(new AnalogTester { val mods = Seq(Module(new AnalogReaderBlackBox), Module(new AnalogReaderWrapper)) - val busWire = Wire(writer.io.bus) + val busWire = Wire(writer.io.bus.cloneType) attach(writer.io.bus, mods(0).io.bus, mods(1).io.bus) mods.foreach(check(_)) }, Seq("/chisel3/AnalogBlackBox.v")) |