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-rw-r--r--src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala11
1 files changed, 8 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index 8e9f9e7e..28b8bc80 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -294,16 +294,21 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
compile {
object Compat {
import Chisel._
- class Foo extends Bundle {
+ class BiDir extends Bundle {
val a = Input(UInt(8.W))
val b = Output(UInt(8.W))
}
+ class Struct extends Bundle {
+ val a = UInt(8.W)
+ }
}
import chisel3._
import Compat._
class Bar extends Bundle {
- val foo1 = new Foo
- val foo2 = Flipped(new Foo)
+ val bidir1 = new BiDir
+ val bidir2 = Flipped(new BiDir)
+ val struct1 = Output(new Struct)
+ val struct2 = Input(new Struct)
}
// Check every connection both ways to see that chisel3 <>'s commutativity holds
class Child extends RawModule {