diff options
| -rw-r--r-- | core/src/main/scala/chisel3/internal/BiConnect.scala | 3 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala | 11 |
2 files changed, 10 insertions, 4 deletions
diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala index fcea4fe2..aa7d7ac3 100644 --- a/core/src/main/scala/chisel3/internal/BiConnect.scala +++ b/core/src/main/scala/chisel3/internal/BiConnect.scala @@ -120,9 +120,10 @@ private[chisel3] object BiConnect { if (notStrict) { // chisel3 <> is commutative but FIRRTL <- is not val flipped = { + import ActualDirection._ // Everything is flipped when it's the port of a child val childPort = left_r._parent.get != context_mod - val isFlipped = left_r.direction == ActualDirection.Bidirectional(ActualDirection.Flipped) + val isFlipped = Seq(Bidirectional(Flipped), Input).contains(left_r.direction) isFlipped ^ childPort } val (newLeft, newRight) = if (flipped) pair.swap else pair diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala index 8e9f9e7e..28b8bc80 100644 --- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala @@ -294,16 +294,21 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec { compile { object Compat { import Chisel._ - class Foo extends Bundle { + class BiDir extends Bundle { val a = Input(UInt(8.W)) val b = Output(UInt(8.W)) } + class Struct extends Bundle { + val a = UInt(8.W) + } } import chisel3._ import Compat._ class Bar extends Bundle { - val foo1 = new Foo - val foo2 = Flipped(new Foo) + val bidir1 = new BiDir + val bidir2 = Flipped(new BiDir) + val struct1 = Output(new Struct) + val struct2 = Input(new Struct) } // Check every connection both ways to see that chisel3 <>'s commutativity holds class Child extends RawModule { |