4 files changed, 72 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 3d98d0a2..ab9d4d62 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -33,10 +33,12 @@ package chiselTests
 import org.scalatest._
 import org.scalatest.prop._
 import org.scalacheck._
+import Chisel._
 import Chisel.testers._
 
 class ChiselPropSpec extends PropSpec with PropertyChecks {
   def execute(t: => BasicTester): Boolean = TesterDriver.execute(t)
+  def elaborate(t: => Module): Circuit = TesterDriver.elaborate(t)
 
   def popCount(n: Long) = n.toBinaryString.count(_=='1')
 
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index cc463600..7562ea2a 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -8,9 +8,9 @@ import Chisel.testers.BasicTester
 class Decoder(bitpats: List[String]) extends Module {
   val io = new Bundle {
     val inst  = UInt(INPUT, 32)
-    val match_idx = UInt(OUTPUT, 5)
+    val matched = Bool(OUTPUT)
   }
-  io.match_idx := Vec(bitpats.map(BitPat(_) === io.inst)).indexWhere{i: Bool => i}
+  io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_)
 }
 
 class DecoderSpec extends ChiselPropSpec {
@@ -20,7 +20,7 @@ class DecoderSpec extends ChiselPropSpec {
     val (cnt, wrap) = Counter(Bool(true), pairs.size)
     val dut = Module(new Decoder(bitpats))
     dut.io.inst := Vec(insts.map(UInt(_)))(cnt)
-    when(dut.io.match_idx != cnt) { io.done := Bool(true); io.error := cnt }
+    when(!dut.io.matched) { io.done := Bool(true); io.error := cnt }
     when(wrap) { io.done := Bool(true) }
   }
 
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
new file mode 100644
index 00000000..0df035c4
--- /dev/null
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -0,0 +1,35 @@
+package chiselTests
+
+import Chisel._
+import org.scalatest._
+import org.scalatest.prop._
+import Chisel.testers.BasicTester
+
+class DirectionHaver extends Module {
+  val io = new Bundle {
+    val in = UInt(INPUT, 32)
+    val out = UInt(OUTPUT, 32)
+  }
+}
+
+class GoodDirection extends DirectionHaver {
+  io.out := UInt(0)
+}
+
+class BadDirection extends DirectionHaver {
+  io.in := UInt(0)
+}
+
+class DirectionSpec extends ChiselPropSpec {
+
+  //TODO: In Chisel3 these are actually FIRRTL errors. Remove from tests?
+
+  property("Outputs should be assignable") {
+    elaborate(new GoodDirection)
+  }
+
+  property("Inputs should not be assignable") {
+    elaborate(new BadDirection)
+  } 
+
+}
diff --git a/src/test/scala/chiselTests/UInt.scala b/src/test/scala/chiselTests/UInt.scala
new file mode 100644
index 00000000..8885c71f
--- /dev/null
+++ b/src/test/scala/chiselTests/UInt.scala
@@ -0,0 +1,32 @@
+package chiselTests
+
+import Chisel._
+import org.scalatest._
+import org.scalatest.prop._
+import Chisel.testers.BasicTester
+
+class GoodBoolConversion extends Module {
+  val io = new Bundle {
+    val u = UInt(1, width = 1).asInput
+    val b = Bool(OUTPUT) 
+  }
+  io.b := io.u.toBool
+}
+
+class BadBoolConversion extends Module {
+  val io = new Bundle {
+    val u = UInt(1, width = 5).asInput
+    val b = Bool(OUTPUT) 
+  }
+  io.b := io.u.toBool
+}
+
+class UIntSpec extends ChiselPropSpec with Matchers {
+  property("Bools can be created from 1 bit UInts") {
+    elaborate(new GoodBoolConversion)
+  }
+
+  property("Bools cannot be created from >1 bit UInts") {
+    a [Exception] should be thrownBy { elaborate(new BadBoolConversion) }
+  } 
+}