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-rw-r--r--src/test/scala/chiselTests/Direction.scala35
1 files changed, 35 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
new file mode 100644
index 00000000..0df035c4
--- /dev/null
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -0,0 +1,35 @@
+package chiselTests
+
+import Chisel._
+import org.scalatest._
+import org.scalatest.prop._
+import Chisel.testers.BasicTester
+
+class DirectionHaver extends Module {
+ val io = new Bundle {
+ val in = UInt(INPUT, 32)
+ val out = UInt(OUTPUT, 32)
+ }
+}
+
+class GoodDirection extends DirectionHaver {
+ io.out := UInt(0)
+}
+
+class BadDirection extends DirectionHaver {
+ io.in := UInt(0)
+}
+
+class DirectionSpec extends ChiselPropSpec {
+
+ //TODO: In Chisel3 these are actually FIRRTL errors. Remove from tests?
+
+ property("Outputs should be assignable") {
+ elaborate(new GoodDirection)
+ }
+
+ property("Inputs should not be assignable") {
+ elaborate(new BadDirection)
+ }
+
+}