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-rw-r--r--src/test/scala/chiselTests/AnalogIntegrationSpec.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
index 952d3872..a3e6e643 100644
--- a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
+++ b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
@@ -19,7 +19,7 @@ class AnalogBlackBoxPort extends Bundle {
// This IO can be used for a single BlackBox or to group multiple
// Has multiple ports for driving and checking but only one shared bus
-class AnalogBlackBoxIO(n: Int) extends Bundle {
+class AnalogBlackBoxIO(val n: Int) extends Bundle {
require(n > 0)
val bus = Analog(32.W)
val port = Vec(n, new AnalogBlackBoxPort)