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| author | Richard Lin | 2018-01-02 13:51:36 -0800 |
|---|---|---|
| committer | GitHub | 2018-01-02 13:51:36 -0800 |
| commit | 678df42aa6bf2f4715be2d051c3c29f058948d0c (patch) | |
| tree | 0b3fb00565e1c442abd7885d490cd4324f02d3fe /src/test/scala/chiselTests/AnalogIntegrationSpec.scala | |
| parent | cb7fcd2b18135230dc40f3c7bb98685e7ffde9d5 (diff) | |
| parent | ade792ee7c5bb718f738f5e4c3886b2e87c68756 (diff) | |
Merge pull request #723 from freechipsproject/autoclonetype
Auto clone type 🦆
Diffstat (limited to 'src/test/scala/chiselTests/AnalogIntegrationSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/AnalogIntegrationSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala index 952d3872..a3e6e643 100644 --- a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala +++ b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala @@ -19,7 +19,7 @@ class AnalogBlackBoxPort extends Bundle { // This IO can be used for a single BlackBox or to group multiple // Has multiple ports for driving and checking but only one shared bus -class AnalogBlackBoxIO(n: Int) extends Bundle { +class AnalogBlackBoxIO(val n: Int) extends Bundle { require(n > 0) val bus = Analog(32.W) val port = Vec(n, new AnalogBlackBoxPort) |