3 files changed, 13 insertions, 6 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 09984722..26ccc09d 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -159,10 +159,16 @@ private class Emitter(circuit: Circuit) {
     * alternative-free statements reset the indent level to the
     * enclosing block upon emission.
     */
-  private def processWhens(cmds: Seq[Command]):
-  Seq[Command] = { cmds.zip(cmds.tail).map({ case (a: WhenEnd, b:
-  AltBegin) => a.copy(hasAlt = true) case (a, b) => a }) ++
-  cmds.lastOption }
+  private def processWhens(cmds: Seq[Command]): Seq[Command] = {
+    if (cmds.isEmpty) {
+      Seq.empty
+    } else {
+      cmds.zip(cmds.tail).map{
+        case (a: WhenEnd, b: AltBegin) => a.copy(hasAlt = true)
+        case (a, b) => a
+      } ++ cmds.lastOption
+    }
+  }
 
   private var indentLevel = 0
   private def newline = "\n" + ("  " * indentLevel)
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index d335f1f1..f31b4015 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -349,6 +349,9 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     a.allElements
   }
   def getModulePorts(m: Module): Seq[Port] = m.getPorts
+  // Invalidate API - a DontCare element for explicit assignment to outputs,
+  //  indicating the signal is intentionally not driven.
+  val DontCare = chisel3.core.DontCare
 
   /** Package for experimental features, which may have their API changed, be removed, etc.
     *
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 451fd039..d35046af 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -44,8 +44,6 @@ object ReadyValidIO {
       */
     def noenq(): Unit = {
       target.valid := false.B
-      // We want the type from the following, not any existing binding.
-      target.bits := Wire(target.bits.cloneType)
     }
 
     /** Assert ready on this port and return the associated data bits.