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-rw-r--r--src/main/scala/chisel3/package.scala3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index d335f1f1..f31b4015 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -349,6 +349,9 @@ package object chisel3 { // scalastyle:ignore package.object.name
a.allElements
}
def getModulePorts(m: Module): Seq[Port] = m.getPorts
+ // Invalidate API - a DontCare element for explicit assignment to outputs,
+ // indicating the signal is intentionally not driven.
+ val DontCare = chisel3.core.DontCare
/** Package for experimental features, which may have their API changed, be removed, etc.
*