diff options
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/chisel3/Driver.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel3/compatibility.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel3/internal/firrtl/Converter.scala | 12 | ||||
| -rw-r--r-- | src/main/scala/chisel3/internal/firrtl/Emitter.scala | 9 | ||||
| -rw-r--r-- | src/main/scala/chisel3/package.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel3/testers/package.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Bitwise.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 4 |
8 files changed, 23 insertions, 18 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala index 77371443..01b9ad1c 100644 --- a/src/main/scala/chisel3/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -178,7 +178,7 @@ object Driver extends BackendCompilationUtilities { * @param dut The device under test * @return An execution result with useful stuff, or failure with message */ - def execute( + def execute( // scalastyle:ignore method.length optionsManager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions, dut: () => RawModule): ChiselExecutionResult = { val circuitOpt = try { @@ -192,7 +192,7 @@ object Driver extends BackendCompilationUtilities { ce.printStackTrace(new PrintWriter(sw)) sw.toString } - Predef.augmentString(stackTrace).lines.foreach(line => println(s"${ErrorLog.errTag} $line")) + Predef.augmentString(stackTrace).lines.foreach(line => println(s"${ErrorLog.errTag} $line")) // scalastyle:ignore regex line.size.limit None } diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 474058be..ad49b095 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -4,7 +4,7 @@ * while moving to the more standard package naming convention `chisel3` (lowercase c). */ -package object Chisel { // scalastyle:ignore package.object.name +package object Chisel { // scalastyle:ignore package.object.name number.of.types number.of.methods import chisel3.internal.firrtl.Width import scala.language.experimental.macros @@ -389,7 +389,7 @@ package object Chisel { // scalastyle:ignore package.object.name // Deprecated as of Chsiel3 @throws(classOf[Exception]) object throwException { - def apply(s: String, t: Throwable = null) = { + def apply(s: String, t: Throwable = null): Nothing = { val xcpt = new Exception(s, t) throw xcpt } diff --git a/src/main/scala/chisel3/internal/firrtl/Converter.scala b/src/main/scala/chisel3/internal/firrtl/Converter.scala index 181bdfe8..ee9d3a99 100644 --- a/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -42,7 +42,7 @@ private[chisel3] object Converter { // TODO // * Memoize? // * Move into the Chisel IR? - def convert(arg: Arg, ctx: Component): fir.Expression = arg match { + def convert(arg: Arg, ctx: Component): fir.Expression = arg match { // scalastyle:ignore cyclomatic.complexity case Node(id) => convert(id.getRef, ctx) case Ref(name) => @@ -54,8 +54,10 @@ private[chisel3] object Converter { case Index(imm, value) => fir.SubAccess(convert(imm, ctx), convert(value, ctx), fir.UnknownType) case ModuleIO(mod, name) => + // scalastyle:off if.brace if (mod eq ctx.id) fir.Reference(name, fir.UnknownType) else fir.SubField(fir.Reference(mod.getRef.name, fir.UnknownType), name, fir.UnknownType) + // scalastyle:on if.brace case u @ ULit(n, UnknownWidth()) => fir.UIntLiteral(n, fir.IntWidth(u.minWidth)) case ULit(n, w) => @@ -75,7 +77,7 @@ private[chisel3] object Converter { } /** Convert Commands that map 1:1 to Statements */ - def convertSimpleCommand(cmd: Command, ctx: Component): Option[fir.Statement] = cmd match { + def convertSimpleCommand(cmd: Command, ctx: Component): Option[fir.Statement] = cmd match { // scalastyle:ignore cyclomatic.complexity line.size.limit case e: DefPrim[_] => val consts = e.args.collect { case ILit(i) => i } val args = e.args.flatMap { @@ -145,8 +147,9 @@ private[chisel3] object Converter { * @param ctx Component (Module) context within which we are translating * @return FIRRTL Statement that is equivalent to the input cmds */ - def convert(cmds: Seq[Command], ctx: Component): fir.Statement = { + def convert(cmds: Seq[Command], ctx: Component): fir.Statement = { // scalastyle:ignore cyclomatic.complexity @tailrec + // scalastyle:off if.brace def rec(acc: Queue[fir.Statement], scope: List[WhenFrame]) (cmds: Seq[Command]): Seq[fir.Statement] = { @@ -190,6 +193,7 @@ private[chisel3] object Converter { } } } + // scalastyle:on if.brace fir.Block(rec(Queue.empty, List.empty)(cmds)) } @@ -209,7 +213,7 @@ private[chisel3] object Converter { case d => d.specifiedDirection } - def extractType(data: Data, clearDir: Boolean = false): fir.Type = data match { + def extractType(data: Data, clearDir: Boolean = false): fir.Type = data match { // scalastyle:ignore cyclomatic.complexity line.size.limit case _: Clock => fir.ClockType case d: EnumType => fir.UIntType(convert(d.width)) case d: UInt => fir.UIntType(convert(d.width)) diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index 68513423..050c8b72 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -26,7 +26,7 @@ private class Emitter(circuit: Circuit) { s"$dirString ${e.id.getRef.name} : ${emitType(e.id, clearDir)}" } - private def emitType(d: Data, clearDir: Boolean = false): String = d match { + private def emitType(d: Data, clearDir: Boolean = false): String = d match { // scalastyle:ignore cyclomatic.complexity line.size.limit case d: Clock => "Clock" case d: chisel3.core.EnumType => s"UInt${d.width}" case d: UInt => s"UInt${d.width}" @@ -55,15 +55,15 @@ private class Emitter(circuit: Circuit) { case d => d.specifiedDirection } - private def emit(e: Command, ctx: Component): String = { + private def emit(e: Command, ctx: Component): String = { // scalastyle:ignore cyclomatic.complexity val firrtlLine = e match { case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})" case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}" case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}" - case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" + case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" // scalastyle:ignore line.size.limit case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]" case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}]" - case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" + case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" // scalastyle:ignore line.size.limit case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}" case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" case e: Attach => e.locs.map(_.fullName(ctx)).mkString("attach (", ", ", ")") @@ -94,6 +94,7 @@ private class Emitter(circuit: Circuit) { s"skip" } firrtlLine + e.sourceInfo.makeMessage(" " + _) + // scalastyle:on line.size.limit } private def emitParam(name: String, p: Param): String = { diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index 6c1ab588..e75184db 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -79,7 +79,7 @@ package object chisel3 { // scalastyle:ignore package.object.name implicit class cloneTypeable[T <: Data](target: T) { @chiselRuntimeDeprecated - @deprecated("chiselCloneType is deprecated, use chiselTypeOf(...) to get the Chisel Type of a hardware object", "chisel3") + @deprecated("chiselCloneType is deprecated, use chiselTypeOf(...) to get the Chisel Type of a hardware object", "chisel3") // scalastyle:ignore line.size.limit def chiselCloneType: T = { target.cloneTypeFull.asInstanceOf[T] } @@ -462,7 +462,7 @@ package object chisel3 { // scalastyle:ignore package.object.name * q2_io.enq <> q1.io.deq * }}} */ - def apply(proto: BaseModule)(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: chisel3.core.CompileOptions): ClonePorts = { + def apply(proto: BaseModule)(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: chisel3.core.CompileOptions): ClonePorts = { // scalastyle:ignore line.size.limit chisel3.core.BaseModule.cloneIORecord(proto) } } diff --git a/src/main/scala/chisel3/testers/package.scala b/src/main/scala/chisel3/testers/package.scala index 649ea3d7..ad1c523d 100644 --- a/src/main/scala/chisel3/testers/package.scala +++ b/src/main/scala/chisel3/testers/package.scala @@ -7,4 +7,4 @@ package chisel3 */ package object testers { -}
\ No newline at end of file +} diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala index 956b8262..1692e083 100644 --- a/src/main/scala/chisel3/util/Bitwise.scala +++ b/src/main/scala/chisel3/util/Bitwise.scala @@ -90,7 +90,7 @@ object Fill { * }}} */ object Reverse { - private def doit(in: UInt, length: Int): UInt = length match { + private def doit(in: UInt, length: Int): UInt = length match { // scalastyle:ignore cyclomatic.complexity case _ if length < 0 => throw new IllegalArgumentException(s"length (=$length) must be nonnegative integer.") case _ if length <= 1 => in case _ if isPow2(length) && length >= 8 && length <= 64 => diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 105b4528..7ab13922 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -95,7 +95,7 @@ object Decoupled */ @chiselName def apply[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = { - require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.") + require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.") // scalastyle:ignore line.size.limit val d = Wire(new DecoupledIO(irr.bits)) d.bits := irr.bits d.valid := irr.valid @@ -126,7 +126,7 @@ object Irrevocable * @note unsafe (and will error) on the consumer (output) side of an DecoupledIO */ def apply[T <: Data](dec: DecoupledIO[T]): IrrevocableIO[T] = { - require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.") + require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.") // scalastyle:ignore line.size.limit val i = Wire(new IrrevocableIO(dec.bits)) dec.bits := i.bits dec.valid := i.valid |