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-rw-r--r--src/main/scala/chisel3/testers/TesterDriver.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index fd3ad9ba..fc71f2b0 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -28,7 +28,7 @@ object TesterDriver extends BackendCompilationUtilities {
// Copy CPP harness and other Verilog sources from resources into files
val cppHarness = new File(path, "top.cpp")
- copyResourceToFile("/top.cpp", cppHarness)
+ copyResourceToFile("/chisel3/top.cpp", cppHarness)
val additionalVFiles = additionalVResources.map((name: String) => {
val mangledResourceName = name.replace("/", "_")
val out = new File(path, mangledResourceName)