diff options
Diffstat (limited to 'src/main/scala/chisel3/util')
| -rw-r--r-- | src/main/scala/chisel3/util/Arbiter.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/BitPat.scala | 8 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 3 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Reg.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 3 |
5 files changed, 4 insertions, 14 deletions
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index d2b29bf9..b99397e2 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -7,8 +7,6 @@ package chisel3.util import chisel3._ import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order -// TODO: remove this once we have CompileOptions threaded through the macro system. -import chisel3.core.ExplicitCompileOptions.NotStrict /** IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs * (selects) at most one. diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala index add40f79..33b9f173 100644 --- a/src/main/scala/chisel3/util/BitPat.scala +++ b/src/main/scala/chisel3/util/BitPat.scala @@ -3,8 +3,8 @@ package chisel3.util import scala.language.experimental.macros - import chisel3._ +import chisel3.core.CompileOptions import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform} object BitPat { @@ -94,7 +94,7 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) { @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3") def != (that: UInt): Bool = macro SourceInfoTransform.thatArg - def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = value.asUInt === (that & mask.asUInt) // scalastyle:ignore method.name - def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that) // scalastyle:ignore method.name - def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that // scalastyle:ignore method.name + def do_=== (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = value.asUInt === (that & mask.asUInt) // scalastyle:ignore method.name + def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = !(this === that) // scalastyle:ignore method.name + def do_!= (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this =/= that // scalastyle:ignore method.name } diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 67da6a17..22532a4d 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -8,9 +8,6 @@ package chisel3.util import chisel3._ import chisel3.internal.naming._ // can't use chisel3_ version because of compile order -// TODO: remove this once we have CompileOptions threaded through the macro system. -import chisel3.core.ExplicitCompileOptions.NotStrict - /** An I/O Bundle containing 'valid' and 'ready' signals that handshake * the transfer of data stored in the 'bits' subfield. * The base protocol implied by the directionality is that the consumer diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala index e85a02fb..34c4d6d8 100644 --- a/src/main/scala/chisel3/util/Reg.scala +++ b/src/main/scala/chisel3/util/Reg.scala @@ -3,8 +3,6 @@ package chisel3.util import chisel3._ -// TODO: remove this once we have CompileOptions threaded through the macro system. -import chisel3.core.ExplicitCompileOptions.NotStrict object RegEnable { /** Returns a register with the specified next, update enable gate, and no reset initialization. diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index 000fff97..8182c475 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -8,9 +8,6 @@ package chisel3.util import chisel3._ import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order -// TODO: remove this once we have CompileOptions threaded through the macro system. -import chisel3.core.ExplicitCompileOptions.NotStrict - /** An Bundle containing data and a signal determining if it is valid */ class Valid[+T <: Data](gen: T) extends Bundle { |
