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-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 67da6a17..22532a4d 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -8,9 +8,6 @@ package chisel3.util
import chisel3._
import chisel3.internal.naming._ // can't use chisel3_ version because of compile order
-// TODO: remove this once we have CompileOptions threaded through the macro system.
-import chisel3.core.ExplicitCompileOptions.NotStrict
-
/** An I/O Bundle containing 'valid' and 'ready' signals that handshake
* the transfer of data stored in the 'bits' subfield.
* The base protocol implied by the directionality is that the consumer